{"id":"https://openalex.org/W2293470376","doi":"https://doi.org/10.1145/2847263.2847341","title":"Just In Time Assembly of Accelerators","display_name":"Just In Time Assembly of Accelerators","publication_year":2016,"publication_date":"2016-02-04","ids":{"openalex":"https://openalex.org/W2293470376","doi":"https://doi.org/10.1145/2847263.2847341","mag":"2293470376"},"language":"en","primary_location":{"id":"doi:10.1145/2847263.2847341","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2847263.2847341","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100543612","display_name":"Sen Ma","orcid":null},"institutions":[{"id":"https://openalex.org/I78715868","display_name":"University of Arkansas at Fayetteville","ror":"https://ror.org/05jbt9m15","country_code":"US","type":"education","lineage":["https://openalex.org/I78715868"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Sen Ma","raw_affiliation_strings":["University of Arkansas, Fayetteville, AR, USA"],"affiliations":[{"raw_affiliation_string":"University of Arkansas, Fayetteville, AR, USA","institution_ids":["https://openalex.org/I78715868"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5013176689","display_name":"Zeyad Aklah","orcid":"https://orcid.org/0000-0002-5617-8946"},"institutions":[{"id":"https://openalex.org/I78715868","display_name":"University of Arkansas at Fayetteville","ror":"https://ror.org/05jbt9m15","country_code":"US","type":"education","lineage":["https://openalex.org/I78715868"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Zeyad Aklah","raw_affiliation_strings":["University of Arkansas, Fayetteville, AR, USA"],"affiliations":[{"raw_affiliation_string":"University of Arkansas, Fayetteville, AR, USA","institution_ids":["https://openalex.org/I78715868"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5062434121","display_name":"David Andrews","orcid":"https://orcid.org/0000-0003-1464-7107"},"institutions":[{"id":"https://openalex.org/I78715868","display_name":"University of Arkansas at Fayetteville","ror":"https://ror.org/05jbt9m15","country_code":"US","type":"education","lineage":["https://openalex.org/I78715868"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"David Andrews","raw_affiliation_strings":["University of Arkansas, Fayetteville, AR, USA"],"affiliations":[{"raw_affiliation_string":"University of Arkansas, Fayetteville, AR, USA","institution_ids":["https://openalex.org/I78715868"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5100543612"],"corresponding_institution_ids":["https://openalex.org/I78715868"],"apc_list":null,"apc_paid":null,"fwci":1.5767,"has_fulltext":false,"cited_by_count":16,"citation_normalized_percentile":{"value":0.81032537,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"173","last_page":"178"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9972000122070312,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.996999979019165,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8409217596054077},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6765969395637512},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.6553224325180054},{"id":"https://openalex.org/keywords/programmer","display_name":"Programmer","score":0.6000638604164124},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.5716542601585388},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4989449977874756},{"id":"https://openalex.org/keywords/interpreter","display_name":"Interpreter","score":0.4781440496444702},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4771444499492645},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.47020986676216125},{"id":"https://openalex.org/keywords/hardware-acceleration","display_name":"Hardware acceleration","score":0.4635336399078369},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4421083629131317},{"id":"https://openalex.org/keywords/vendor","display_name":"Vendor","score":0.42143717408180237},{"id":"https://openalex.org/keywords/toolchain","display_name":"Toolchain","score":0.4195364713668823},{"id":"https://openalex.org/keywords/domain-specific-language","display_name":"Domain-specific language","score":0.4110146164894104},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.33825621008872986}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8409217596054077},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6765969395637512},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.6553224325180054},{"id":"https://openalex.org/C2778514511","wikidata":"https://www.wikidata.org/wiki/Q1374194","display_name":"Programmer","level":2,"score":0.6000638604164124},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.5716542601585388},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4989449977874756},{"id":"https://openalex.org/C122783720","wikidata":"https://www.wikidata.org/wiki/Q183065","display_name":"Interpreter","level":2,"score":0.4781440496444702},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4771444499492645},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.47020986676216125},{"id":"https://openalex.org/C13164978","wikidata":"https://www.wikidata.org/wiki/Q600158","display_name":"Hardware acceleration","level":3,"score":0.4635336399078369},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4421083629131317},{"id":"https://openalex.org/C2777338717","wikidata":"https://www.wikidata.org/wiki/Q1762621","display_name":"Vendor","level":2,"score":0.42143717408180237},{"id":"https://openalex.org/C2777062904","wikidata":"https://www.wikidata.org/wiki/Q545406","display_name":"Toolchain","level":3,"score":0.4195364713668823},{"id":"https://openalex.org/C135257023","wikidata":"https://www.wikidata.org/wiki/Q691358","display_name":"Domain-specific language","level":2,"score":0.4110146164894104},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.33825621008872986},{"id":"https://openalex.org/C144133560","wikidata":"https://www.wikidata.org/wiki/Q4830453","display_name":"Business","level":0,"score":0.0},{"id":"https://openalex.org/C162853370","wikidata":"https://www.wikidata.org/wiki/Q39809","display_name":"Marketing","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2847263.2847341","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2847263.2847341","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.46000000834465027,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1631634011","https://openalex.org/W1983394510","https://openalex.org/W1997358129","https://openalex.org/W2052930524","https://openalex.org/W2071630526","https://openalex.org/W2081418732","https://openalex.org/W2097959379","https://openalex.org/W2105263017","https://openalex.org/W2113263062","https://openalex.org/W2153580689","https://openalex.org/W2328536951","https://openalex.org/W4255673994"],"related_works":["https://openalex.org/W4233332105","https://openalex.org/W156394931","https://openalex.org/W2060824677","https://openalex.org/W2079450985","https://openalex.org/W2121863986","https://openalex.org/W2055606014","https://openalex.org/W3115530580","https://openalex.org/W2071630526","https://openalex.org/W2622392763","https://openalex.org/W2390254310"],"abstract_inverted_index":{"Despite":[0],"the":[1,12,37,52,77,86,94,100,121,148,160,165],"significant":[2],"advancements":[3],"that":[4,30,71,103,129],"have":[5],"been":[6],"made":[7],"in":[8],"High":[9],"Level":[10],"Synthesis,":[11],"reconfigurable":[13,140],"computing":[14],"community":[15],"has":[16],"failed":[17],"at":[18,142],"getting":[19],"programmers":[20,32,88],"to":[21,39,54,153,159,163,187],"use":[22],"Field":[23],"Programmable":[24],"Gate":[25],"Arrays":[26],"(FPGAs).":[27],"Existing":[28],"barriers":[29,74],"prevent":[31],"from":[33,85],"using":[34,120],"FPGAs":[35],"include":[36],"need":[38],"work":[40],"within":[41,133],"vendor":[42],"specific":[43],"CAD":[44],"tools,":[45],"knowledge":[46],"of":[47,76,93,138],"hardware":[48,117,131,151],"programming":[49,101],"models,":[50],"and":[51,61,184],"requirement":[53],"pass":[55],"each":[56],"design":[57,78],"through":[58],"synthesis,":[59],"place":[60],"route.":[62],"In":[63],"this":[64],"paper":[65],"we":[66],"present":[67],"a":[68,105,134,173,189],"new":[69],"approach":[70,149,175],"takes":[72],"these":[73],"out":[75],"flows":[79],"for":[80,181],"programmers.":[81],"Synthesis":[82],"is":[83,127],"eliminated":[84],"application":[87],"path":[89],"by":[90],"becoming":[91],"part":[92],"initial":[95],"coding":[96],"process":[97],"when":[98,119],"creating":[99,114],"patterns":[102],"define":[104],"Domain":[106],"Specific":[107],"Language.":[108],"Programmers":[109],"see":[110],"no":[111],"difference":[112],"between":[113],"software":[115],"or":[116],"functionality":[118],"DSL.":[122],"A":[123],"run":[124,143],"time":[125,161],"interpreter":[126],"introduced":[128],"assembles":[130],"accelerators":[132,152],"configurable":[135],"tile":[136],"array":[137],"partially":[139],"slots":[141],"time.":[144],"Initial":[145,168],"results":[146,170],"show":[147,172],"allows":[150],"be":[154],"compiled":[155],"100x":[156],"faster":[157],"compared":[158,186],"required":[162],"synthesize":[164],"same":[166],"functionality.":[167],"performance":[169,180],"further":[171],"compilation/interpretation":[174],"can":[176],"achieve":[177],"approximately":[178],"equivalent":[179],"matrix":[182],"operations":[183],"filtering":[185],"synthesizing":[188],"custom":[190],"accelerator.":[191]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":4},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}