{"id":"https://openalex.org/W2295840435","doi":"https://doi.org/10.1145/2847263.2847323","title":"Floorplanning of Partially Reconfigurable Design on Heterogeneous FPGA (Abstract Only)","display_name":"Floorplanning of Partially Reconfigurable Design on Heterogeneous FPGA (Abstract Only)","publication_year":2016,"publication_date":"2016-02-04","ids":{"openalex":"https://openalex.org/W2295840435","doi":"https://doi.org/10.1145/2847263.2847323","mag":"2295840435"},"language":"en","primary_location":{"id":"doi:10.1145/2847263.2847323","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2847263.2847323","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["arxiv","crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://arxiv.org/pdf/2011.11716","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":null,"display_name":"Pingakshya Goswami","orcid":null},"institutions":[{"id":"https://openalex.org/I162577319","display_name":"The University of Texas at Dallas","ror":"https://ror.org/049emcs32","country_code":"US","type":"education","lineage":["https://openalex.org/I162577319"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Pingakshya Goswami","raw_affiliation_strings":["University of Texas at Dallas, Richardson, TX, USA"],"affiliations":[{"raw_affiliation_string":"University of Texas at Dallas, Richardson, TX, USA","institution_ids":["https://openalex.org/I162577319"]}]},{"author_position":"last","author":{"id":null,"display_name":"Dinesh Bhatia","orcid":null},"institutions":[{"id":"https://openalex.org/I162577319","display_name":"The University of Texas at Dallas","ror":"https://ror.org/049emcs32","country_code":"US","type":"education","lineage":["https://openalex.org/I162577319"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Dinesh Bhatia","raw_affiliation_strings":["University of Texas at Dallas, Richardson, TX, USA"],"affiliations":[{"raw_affiliation_string":"University of Texas at Dallas, Richardson, TX, USA","institution_ids":["https://openalex.org/I162577319"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I162577319"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.0078312,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"275","last_page":"275"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/floorplan","display_name":"Floorplan","score":0.983299970626831},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7511000037193298},{"id":"https://openalex.org/keywords/simulated-annealing","display_name":"Simulated annealing","score":0.7188000082969666},{"id":"https://openalex.org/keywords/sorting","display_name":"Sorting","score":0.5267000198364258},{"id":"https://openalex.org/keywords/integrated-circuit-layout","display_name":"Integrated circuit layout","score":0.45019999146461487},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.400299996137619},{"id":"https://openalex.org/keywords/preprocessor","display_name":"Preprocessor","score":0.38359999656677246},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.3513000011444092},{"id":"https://openalex.org/keywords/sorting-algorithm","display_name":"Sorting algorithm","score":0.3012000024318695}],"concepts":[{"id":"https://openalex.org/C130145326","wikidata":"https://www.wikidata.org/wiki/Q1553985","display_name":"Floorplan","level":2,"score":0.983299970626831},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7511000037193298},{"id":"https://openalex.org/C126980161","wikidata":"https://www.wikidata.org/wiki/Q863783","display_name":"Simulated annealing","level":2,"score":0.7188000082969666},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5928000211715698},{"id":"https://openalex.org/C111696304","wikidata":"https://www.wikidata.org/wiki/Q2303697","display_name":"Sorting","level":2,"score":0.5267000198364258},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.45019999146461487},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4083999991416931},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.400299996137619},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3853999972343445},{"id":"https://openalex.org/C34736171","wikidata":"https://www.wikidata.org/wiki/Q918333","display_name":"Preprocessor","level":2,"score":0.38359999656677246},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.3513000011444092},{"id":"https://openalex.org/C108094655","wikidata":"https://www.wikidata.org/wiki/Q181593","display_name":"Sorting algorithm","level":3,"score":0.3012000024318695},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2851000130176544},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.2833999991416931},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.2806999981403351},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.27709999680519104},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.2770000100135803},{"id":"https://openalex.org/C127879752","wikidata":"https://www.wikidata.org/wiki/Q3390760","display_name":"Place and route","level":3,"score":0.2759999930858612},{"id":"https://openalex.org/C106516650","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm design","level":2,"score":0.2614000141620636},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.2597000002861023},{"id":"https://openalex.org/C114237110","wikidata":"https://www.wikidata.org/wiki/Q114901","display_name":"Gate array","level":3,"score":0.25619998574256897},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.2551000118255615},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.25440001487731934},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.25200000405311584},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.2506999969482422},{"id":"https://openalex.org/C66882249","wikidata":"https://www.wikidata.org/wiki/Q169336","display_name":"Homogeneous","level":2,"score":0.25029999017715454}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/2847263.2847323","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2847263.2847323","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"},{"id":"pmh:oai:arXiv.org:2011.11716","is_oa":true,"landing_page_url":"http://arxiv.org/abs/2011.11716","pdf_url":"https://arxiv.org/pdf/2011.11716","source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"text"}],"best_oa_location":{"id":"pmh:oai:arXiv.org:2011.11716","is_oa":true,"landing_page_url":"http://arxiv.org/abs/2011.11716","pdf_url":"https://arxiv.org/pdf/2011.11716","source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"text"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":[],"abstract_inverted_index":{"The":[0,67,164],"floorplanning":[1,18,90,218],"problem":[2,19],"in":[3,48,190,197,259],"FPGA":[4,62,115,178],"has":[5,20,30],"been":[6,21,31],"a":[7,14,42,79,93,100,119,147,159,225,237,254],"topic":[8],"of":[9,57,110,124,127,154,166,224,232,261,272],"research":[10],"for":[11,24,33,44,88,96,107],"more":[12],"than":[13],"decade.":[15],"Although":[16],"the":[17,55,61,114,191,198,204,217,222,242,247,268,273,285],"thoroughly":[22],"explored":[23],"homogeneous":[25],"FPGAs,":[26],"very":[27],"less":[28],"work":[29],"done":[32],"heterogeneous":[34,49],"FPGAs.":[35],"In":[36,141],"this":[37,135,142],"paper,":[38],"we":[39,144,208],"have":[40,181],"designed":[41],"floorplanner":[43,68,168,185,211],"partially":[45,226],"reconfigurable":[46,227,234,269],"design":[47],"FPGAs":[50],"which":[51,91,122,230],"takes":[52],"into":[53],"consideration":[54],"diversity":[56],"resources":[58],"present":[59],"inside":[60,113],"device":[63],"and":[64,130,133,157,193,246,275,283],"their":[65],"locations.":[66],"is":[69,92,105,169,239,257],"based":[70,81],"on":[71,174],"fixed":[72],"outline":[73],"simulated":[74,97,139],"annealing":[75],"algorithm.":[76],"We":[77,117,180,220],"proposed":[78,106,184],"priority":[80],"sorting":[82],"algorithm":[83,104],"mimicking":[84],"Olympic":[85],"Medal":[86],"Tally":[87],"initial":[89],"preprocessing":[94],"step":[95],"annealing.":[98,140],"Also,":[99],"White":[101],"Space":[102],"detection":[103],"efficient":[108],"management":[109],"white":[111],"space":[112],"device.":[116],"defined":[118],"cost":[120,136],"function,":[121],"consists":[123,231],"weighed":[125],"sum":[126],"wirelength,":[128],"area":[129,265],"resource":[131,155],"wastage,":[132],"minimized":[134],"function":[137],"using":[138,171],"work,":[143],"also":[145],"described":[146],"method":[148,160],"to":[149,161,215,281],"calculate":[150],"two":[151],"different":[152],"types":[153],"wastage":[156],"suggested":[158],"reduce":[162],"it.":[163],"performance":[165],"our":[167,183,210,252],"evaluated":[170],"MCNC":[172],"benchmarks":[173],"Xilinx":[175,213],"Virtex":[176],"5":[177],"architecture.":[179],"compared":[182],"with":[186,212],"other":[187],"results":[188],"reported":[189],"literature":[192],"observed":[194,258],"substantial":[195],"improvement":[196,256],"overall":[199],"wirelength":[200],"as":[201,203],"well":[202],"execution":[205],"time.":[206],"Finally,":[207],"integrated":[209],"PlanAhead":[214,280],"automate":[216],"process.":[219],"generate":[221],"floorplan":[223,245,249],"median":[228],"filter,":[229],"seven":[233],"regions.":[235],"When":[236],"comparison":[238],"made":[240],"between":[241],"manually":[243],"generated":[244,250],"automatic":[248],"by":[251,267,279],"tool,":[253],"significant":[255],"terms":[260],"parameters":[262],"like":[263],"total":[264,276],"occupied":[266],"regions,":[270],"frequency":[271],"operation":[274],"time":[277],"required":[278],"place":[282],"route":[284],"design.":[286]},"counts_by_year":[{"year":2023,"cited_by_count":1}],"updated_date":"2026-03-07T16:01:11.037858","created_date":"2016-06-24T00:00:00"}