{"id":"https://openalex.org/W2293388187","doi":"https://doi.org/10.1145/2847263.2847322","title":"An Activity Aware Placement Approach For 3D FPGAs (Abstract Only)","display_name":"An Activity Aware Placement Approach For 3D FPGAs (Abstract Only)","publication_year":2016,"publication_date":"2016-02-04","ids":{"openalex":"https://openalex.org/W2293388187","doi":"https://doi.org/10.1145/2847263.2847322","mag":"2293388187"},"language":"en","primary_location":{"id":"doi:10.1145/2847263.2847322","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2847263.2847322","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5013669463","display_name":"Girish Deshpande","orcid":null},"institutions":[{"id":"https://openalex.org/I162577319","display_name":"The University of Texas at Dallas","ror":"https://ror.org/049emcs32","country_code":"US","type":"education","lineage":["https://openalex.org/I162577319"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Girish Deshpande","raw_affiliation_strings":["University of Texas at Dallas, Richardson, TX, USA"],"affiliations":[{"raw_affiliation_string":"University of Texas at Dallas, Richardson, TX, USA","institution_ids":["https://openalex.org/I162577319"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5069692759","display_name":"Dinesh Bhatia","orcid":"https://orcid.org/0000-0002-5019-7417"},"institutions":[{"id":"https://openalex.org/I162577319","display_name":"The University of Texas at Dallas","ror":"https://ror.org/049emcs32","country_code":"US","type":"education","lineage":["https://openalex.org/I162577319"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Dinesh Bhatia","raw_affiliation_strings":["University of Texas at Dallas, Richardson, TX, USA"],"affiliations":[{"raw_affiliation_string":"University of Texas at Dallas, Richardson, TX, USA","institution_ids":["https://openalex.org/I162577319"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5013669463"],"corresponding_institution_ids":["https://openalex.org/I162577319"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.00675199,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"277","last_page":"277"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9962000250816345,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7877038717269897},{"id":"https://openalex.org/keywords/three-dimensional-integrated-circuit","display_name":"Three-dimensional integrated circuit","score":0.7131643891334534},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6860213279724121},{"id":"https://openalex.org/keywords/placement","display_name":"Placement","score":0.4892716109752655},{"id":"https://openalex.org/keywords/layer","display_name":"Layer (electronics)","score":0.4752880334854126},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.46491652727127075},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.44826069474220276},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.43287914991378784},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.36377114057540894},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.35217761993408203},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.3224809765815735},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.24982380867004395},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.10978645086288452},{"id":"https://openalex.org/keywords/nanotechnology","display_name":"Nanotechnology","score":0.10153430700302124},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08722436428070068}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7877038717269897},{"id":"https://openalex.org/C59088047","wikidata":"https://www.wikidata.org/wiki/Q229370","display_name":"Three-dimensional integrated circuit","level":3,"score":0.7131643891334534},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6860213279724121},{"id":"https://openalex.org/C117690923","wikidata":"https://www.wikidata.org/wiki/Q1484784","display_name":"Placement","level":4,"score":0.4892716109752655},{"id":"https://openalex.org/C2779227376","wikidata":"https://www.wikidata.org/wiki/Q6505497","display_name":"Layer (electronics)","level":2,"score":0.4752880334854126},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.46491652727127075},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.44826069474220276},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.43287914991378784},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.36377114057540894},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.35217761993408203},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.3224809765815735},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.24982380867004395},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.10978645086288452},{"id":"https://openalex.org/C171250308","wikidata":"https://www.wikidata.org/wiki/Q11468","display_name":"Nanotechnology","level":1,"score":0.10153430700302124},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08722436428070068}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2847263.2847322","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2847263.2847322","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6299999952316284,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2132668926","https://openalex.org/W2547355295","https://openalex.org/W2042759115","https://openalex.org/W2159053194","https://openalex.org/W1964677779","https://openalex.org/W4318224776","https://openalex.org/W2169510384","https://openalex.org/W2155675690","https://openalex.org/W2099105040","https://openalex.org/W1563562883"],"abstract_inverted_index":{"In":[0],"order":[1,47],"to":[2,48,98,143,162,179,201,263],"cope":[3],"with":[4,208],"increasing":[5],"demand":[6],"for":[7,105],"higher":[8,184,209],"logic":[9],"densities":[10,186],"and":[11,23,67,92,103,137,205,224,245],"shrinking":[12],"feature":[13],"sizes,":[14],"there":[15],"has":[16,58,75],"been":[17,39,59,76],"a":[18,111,148,164,220,236,264],"concerted":[19],"effort":[20],"by":[21],"academia":[22],"industry":[24],"towards":[25],"the":[26,42,79,83,90,121,156,173,188,193,202,229,258],"design":[27],"of":[28,55,85,116,159,170,192,251],"three":[29],"dimensional":[30],"integrated":[31],"circuits":[32],"(3D":[33],"ICs).":[34],"Various":[35],"architectural":[36,91],"approaches":[37],"have":[38],"investigated":[40],"over":[41],"past":[43],"few":[44],"years":[45],"in":[46,78,120,219],"realize":[49],"functional":[50],"3D":[51,86,108,129,149,239],"ICs.":[52],"A":[53],"majority":[54],"such":[56,63],"research":[57],"focused":[60],"on":[61,82,128,135,172,187,212,228,235,246,257],"devices":[62],"as":[64,261],"memories,":[65],"caches":[66],"other":[68],"application":[69],"specific":[70],"circuits.":[71],"Not":[72],"much":[73],"work":[74,96],"done":[77],"FPGA":[80,130,240],"community":[81],"exploration":[84],"FPGAs":[87,109],"both":[88],"at":[89,100],"EDA":[93],"levels.":[94],"This":[95,175,231],"aims":[97],"look":[99],"placement":[101,131,176],"methodologies":[102],"metrics":[104],"island":[106],"style":[107],"from":[110],"thermal":[112],"perspective.":[113],"The":[114,195],"novelty":[115],"our":[117],"approach":[118],"lies":[119],"fact":[122],"that":[123,151,266],"unlike":[124],"previous":[125],"related":[126],"works":[127],"which":[132,182],"rely":[133],"solely":[134],"wirelength":[136],"TSV":[138],"(Through":[139],"Silicon":[140],"Via)-count":[141],"minimization":[142],"evaluate":[144],"placement,":[145],"we":[146],"propose":[147],"placer":[150,232,265],"also":[152],"takes":[153],"into":[154],"consideration,":[155],"transition":[157,185,270],"density":[158,271],"each":[160],"net":[161],"ensure":[163],"more":[165,221],"thermally":[166],"balanced":[167],"spatial":[168],"distribution":[169],"nets":[171,181,207,254],"chip.":[174,230],"methodology":[177],"tries":[178],"place":[180],"exhibit":[183],"lower":[189],"most":[190],"layer":[191,197,214,238,260],"FPGA.":[194],"lowest":[196,259],"is":[198],"typically":[199],"closest":[200],"heat":[203,217],"sink":[204],"placing":[206],"switching":[210],"activity":[211,253],"this":[213],"will":[215],"aid":[216],"dissipation":[218],"effective":[222],"manner":[223],"reduce":[225],"hot":[226],"spots":[227],"was":[233],"tested":[234],"four":[237],"model":[241],"using":[242],"MCNC":[243],"benchmarks":[244],"average,":[247],"around":[248],"40":[249],"%":[250],"high":[252],"were":[255],"placed":[256],"compared":[262],"did":[267],"not":[268],"employ":[269],"based":[272],"cost":[273],"scaling":[274],"during":[275],"placement.":[276]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}