{"id":"https://openalex.org/W2260932751","doi":"https://doi.org/10.1145/2847263.2847314","title":"A Full-Capacity Local RoutingArchitecture for FPGAs (Abstract Only)","display_name":"A Full-Capacity Local RoutingArchitecture for FPGAs (Abstract Only)","publication_year":2016,"publication_date":"2016-02-04","ids":{"openalex":"https://openalex.org/W2260932751","doi":"https://doi.org/10.1145/2847263.2847314","mag":"2260932751"},"language":"en","primary_location":{"id":"doi:10.1145/2847263.2847314","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2847263.2847314","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://infoscience.epfl.ch/record/213817/files/XT_FPGA16.pdf","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5103004961","display_name":"Xifan Tang","orcid":"https://orcid.org/0000-0003-2203-3981"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":true,"raw_author_name":"Xifan Tang","raw_affiliation_strings":["EPFL, Lausanne, Switzerland"],"affiliations":[{"raw_affiliation_string":"EPFL, Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5002568331","display_name":"Pierre\u2010Emmanuel Gaillardon","orcid":"https://orcid.org/0000-0003-3634-3999"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Pierre-Emmanuel Gaillardon","raw_affiliation_strings":["EPFL, Lausanne, Switzerland"],"affiliations":[{"raw_affiliation_string":"EPFL, Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5072927296","display_name":"Giovanni De Micheli","orcid":"https://orcid.org/0000-0002-7827-3215"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Giovanni De Micheli","raw_affiliation_strings":["EPFL, Lausanne, Switzerland"],"affiliations":[{"raw_affiliation_string":"EPFL, Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5103004961"],"corresponding_institution_ids":["https://openalex.org/I5124864"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.00268348,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"281","last_page":"281"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6749356985092163},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.6377442479133606},{"id":"https://openalex.org/keywords/router","display_name":"Router","score":0.516156792640686},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.4927542507648468},{"id":"https://openalex.org/keywords/crossbar-switch","display_name":"Crossbar switch","score":0.47163698077201843},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4626978039741516},{"id":"https://openalex.org/keywords/logic-block","display_name":"Logic block","score":0.4292733073234558},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.38299834728240967},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.35417497158050537},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.3326183557510376},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.25045061111450195}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6749356985092163},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.6377442479133606},{"id":"https://openalex.org/C2775896111","wikidata":"https://www.wikidata.org/wiki/Q642560","display_name":"Router","level":2,"score":0.516156792640686},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.4927542507648468},{"id":"https://openalex.org/C29984679","wikidata":"https://www.wikidata.org/wiki/Q1929149","display_name":"Crossbar switch","level":2,"score":0.47163698077201843},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4626978039741516},{"id":"https://openalex.org/C2778325283","wikidata":"https://www.wikidata.org/wiki/Q1125244","display_name":"Logic block","level":3,"score":0.4292733073234558},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.38299834728240967},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.35417497158050537},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.3326183557510376},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.25045061111450195},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/2847263.2847314","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2847263.2847314","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"},{"id":"pmh:oai:infoscience.tind.io:213817","is_oa":true,"landing_page_url":"http://infoscience.epfl.ch/record/213817","pdf_url":"https://infoscience.epfl.ch/record/213817/files/XT_FPGA16.pdf","source":{"id":"https://openalex.org/S4306400487","display_name":"Infoscience (Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"conference proceedings"}],"best_oa_location":{"id":"pmh:oai:infoscience.tind.io:213817","is_oa":true,"landing_page_url":"http://infoscience.epfl.ch/record/213817","pdf_url":"https://infoscience.epfl.ch/record/213817/files/XT_FPGA16.pdf","source":{"id":"https://openalex.org/S4306400487","display_name":"Infoscience (Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"conference proceedings"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2260932751.pdf","grobid_xml":"https://content.openalex.org/works/W2260932751.grobid-xml"},"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2352167000","https://openalex.org/W3146360095","https://openalex.org/W2127180614","https://openalex.org/W2014521732","https://openalex.org/W3012528295","https://openalex.org/W2024574431","https://openalex.org/W2167711148","https://openalex.org/W2387100797","https://openalex.org/W4235531327","https://openalex.org/W1603115038"],"abstract_inverted_index":{"Reconfigurable":[0],"systems":[1],"employ":[2,15],"highly-routable":[3],"local":[4,25,86,128,187,210,249,270],"routing":[5,26,87,188,211,250,259,271],"architecture":[6,27,88,189,212,237,251,272],"to":[7,28,65,76,108,118,155,174],"interconnect":[8,109],"generic":[9],"fine-grain":[10,114],"logic":[11,49,92,177,206],"blocks.":[12],"Commercial":[13],"FPGAs":[14],"50%":[16],"sparse":[17],"crossbars":[18,22,107,141,154,166],"rather":[19],"than":[20],"fully-connected":[21,135,153],"in":[23,126,148,281],"their":[24],"trade":[29],"off":[30],"between":[31],"the":[32,37,42,52,55,57,60,77,101,110,113,119,123,127,145,151,162,171,176,180,185,191,194,203,208,214,247,268,274],"area":[33,163,199,260],"and":[34,48,97,136,240,257,278],"routability":[35,47,159,192,275],"of":[36,54,59,71,100,112,122,134,150,179,193,218,245,276],"Logic":[38,115],"Blocks":[39],"(LBs).":[40],"While":[41],"input":[43,96,172],"crossbar":[44],"provides":[45],"good":[46],"equivalence":[50,93,178],"for":[51,144,170],"inputs":[53],"LB,":[56],"outputs":[58,111,204],"LBs":[61],"are":[62,142,167],"typically":[63],"assigned":[64],"a":[66,84,132,157,183,234,242,286],"physical":[67],"location.":[68],"This":[69],"lack":[70],"flexibility":[72],"brings":[73,279],"strong":[74],"constraints":[75],"global":[78],"net":[79],"router.":[80],"Here,":[81],"we":[82,104,130],"propose":[83],"novel":[85,186,248,269],"that":[89,224],"guarantees":[90],"full":[91,158,215],"on":[94,228,265,285],"all":[95],"output":[98,120],"pins":[99,121],"LBs.":[102,124],"First,":[103],"introduce":[105],"full-capacity":[106,137,140],"Elements":[116],"(LEs)":[117],"Second,":[125],"routing,":[129],"use":[131],"combination":[133],"crossbars.":[138],"The":[139],"used":[143],"feedback":[146],"connections":[147,173],"place":[149],"standard":[152],"ensure":[156],"while":[160],"reducing":[161],"footprint.":[164],"Fully-connected":[165],"still":[168],"employed":[169],"maintain":[175],"inputs.":[181],"As":[182],"result,":[184],"enhances":[190,273],"LB":[195],"clusters":[196],"without":[197,225],"any":[198,226],"overhead.":[200],"By":[201],"granting":[202],"with":[205,261],"equivalence,":[207],"proposed":[209],"unlocks":[213],"optimization":[216],"potential":[217],"FPGA":[219,236,288],"routers.":[220],"Architectural":[221],"simulations":[222],"show":[223],"modification":[227],"Verilog-to-Routing":[229],"(VTR)":[230],"tool":[231],"suites,":[232],"when":[233],"commercial":[235],"is":[238],"considered":[239],"over":[241],"wide":[243],"set":[244],"benchmarks,":[246],"can":[252],"reduce":[253],"10%":[254,262],"channel":[255],"width":[256],"11%":[258],"less":[263],"area\u00d7delay\u00d7power":[264],"average.":[266],"Therefore,":[267],"FPGA,":[277],"opportunities":[280],"realizing":[282],"larger":[283],"implementations":[284],"single":[287],"chip.":[289]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2016-06-24T00:00:00"}
