{"id":"https://openalex.org/W2294283285","doi":"https://doi.org/10.1145/2847263.2847307","title":"An FPGA-SOC Based Accelerating Solution for N-body Simulations in MOND (Abstract Only)","display_name":"An FPGA-SOC Based Accelerating Solution for N-body Simulations in MOND (Abstract Only)","publication_year":2016,"publication_date":"2016-02-04","ids":{"openalex":"https://openalex.org/W2294283285","doi":"https://doi.org/10.1145/2847263.2847307","mag":"2294283285"},"language":"en","primary_location":{"id":"doi:10.1145/2847263.2847307","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2847263.2847307","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100625833","display_name":"Bo Peng","orcid":"https://orcid.org/0000-0002-8800-5695"},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Bo Peng","raw_affiliation_strings":["School of Physical Sciences, USTC, Hefei, China"],"affiliations":[{"raw_affiliation_string":"School of Physical Sciences, USTC, Hefei, China","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100734913","display_name":"Tianqi Wang","orcid":"https://orcid.org/0000-0002-5921-6565"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Tianqi Wang","raw_affiliation_strings":["School of Physical Sciences, USTC, Hefei, China"],"affiliations":[{"raw_affiliation_string":"School of Physical Sciences, USTC, Hefei, China","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5046555671","display_name":"Xi Jin","orcid":"https://orcid.org/0000-0003-2087-0698"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Xi Jin","raw_affiliation_strings":["School of Physical Sciences, USTC, Hefei, China"],"affiliations":[{"raw_affiliation_string":"School of Physical Sciences, USTC, Hefei, China","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5013789724","display_name":"Chuanjun Wang","orcid":"https://orcid.org/0000-0002-8257-0781"},"institutions":[{"id":"https://openalex.org/I19820366","display_name":"Chinese Academy of Sciences","ror":"https://ror.org/034t30j35","country_code":"CN","type":"funder","lineage":["https://openalex.org/I19820366"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Chuanjun Wang","raw_affiliation_strings":["Chinese Academy of Sciences, Kunming, China"],"affiliations":[{"raw_affiliation_string":"Chinese Academy of Sciences, Kunming, China","institution_ids":["https://openalex.org/I19820366"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5100625833"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.01363551,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"278","last_page":"278"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.996399998664856,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.996399998664856,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13650","display_name":"Computational Physics and Python Applications","score":0.982200026512146,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9787999987602234,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/bottleneck","display_name":"Bottleneck","score":0.826412558555603},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8237044215202332},{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.7498641610145569},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6635205745697021},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.543297529220581},{"id":"https://openalex.org/keywords/pipeline-transport","display_name":"Pipeline transport","score":0.44514697790145874},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4434615671634674},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.4259507656097412},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3937583267688751},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1310519576072693}],"concepts":[{"id":"https://openalex.org/C2780513914","wikidata":"https://www.wikidata.org/wiki/Q18210350","display_name":"Bottleneck","level":2,"score":0.826412558555603},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8237044215202332},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.7498641610145569},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6635205745697021},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.543297529220581},{"id":"https://openalex.org/C175309249","wikidata":"https://www.wikidata.org/wiki/Q725864","display_name":"Pipeline transport","level":2,"score":0.44514697790145874},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4434615671634674},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.4259507656097412},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3937583267688751},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1310519576072693},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C87717796","wikidata":"https://www.wikidata.org/wiki/Q146326","display_name":"Environmental engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2847263.2847307","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2847263.2847307","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Decent work and economic growth","id":"https://metadata.un.org/sdg/8","score":0.550000011920929}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W4380433113","https://openalex.org/W4386072068","https://openalex.org/W252339960","https://openalex.org/W2390529043","https://openalex.org/W2378320433","https://openalex.org/W2358343511","https://openalex.org/W2051877971","https://openalex.org/W1970117064","https://openalex.org/W1787170397","https://openalex.org/W4292347844"],"abstract_inverted_index":{"Modified":[0],"Newtonian":[1],"dynamics":[2],"(MOND)":[3],"has":[4,149],"shown":[5],"a":[6,10,20,71,150],"great":[7],"success":[8],"as":[9,94],"modified-potential":[11],"theory":[12],"of":[13,63,88,101,109,153],"gravity.":[14],"In":[15],"this":[16],"paper,":[17],"we":[18,69],"present":[19],"highly":[21],"integrated":[22,130],"accelerating":[23,147],"solution":[24,46,148],"for":[25,49],"N-body":[26],"MOND":[27],"simulations.":[28],"By":[29],"using":[30],"the":[31,60,75,79,86,97,105,116,135,139],"FPGA-SoC,":[32],"which":[33,78],"integrates":[34],"both":[35,167],"FPGA":[36],"and":[37,54,138,171],"SOC":[38],"(system":[39],"on":[40,66,104,118],"chip)":[41],"in":[42,77,131,166],"one":[43,67],"chip,":[44],"our":[45,146,161],"exhibits":[47],"potential":[48,64],"better":[50,165],"performance,":[51],"higher":[52],"integration,":[53],"lower":[55],"power":[56],"consumption.":[57],"To":[58],"handle":[59],"calculation":[61,81],"bottleneck":[62,117],"summation,":[65],"hand,":[68,107],"develop":[70],"strategy":[72],"to":[73,95,114],"simplify":[74],"pipeline,":[76,137],"square":[80],"task":[82],"is":[83,142,163],"conducted":[84],"by":[85],"DSP48E1":[87],"Xilinx":[89],"7":[90],"series":[91],"FPGAs,":[92],"so":[93],"reduce":[96],"logic":[98],"resource":[99],"consumption":[100],"each":[102],"pipeline;":[103],"other":[106],"advantages":[108,154],"particle-mesh":[110],"scheme":[111],"are":[112],"taken":[113],"overcome":[115],"bandwidth.":[119],"Our":[120],"experiment":[121],"results":[122],"show":[123],"that":[124],"2":[125],"more":[126],"pipelines":[127],"can":[128],"be":[129],"Zynq-7020":[132],"FPGA-SoC":[133],"with":[134,159],"simplified":[136],"bandwidth":[140],"requirement":[141],"reduced":[143],"significantly.":[144],"Furthermore,":[145],"full":[151],"range":[152],"over":[155],"different":[156],"processors.":[157],"Compared":[158],"GPU,":[160],"work":[162],"about":[164],"performance":[168,172],"per":[169,173],"Watt":[170],"cost.":[174]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}