{"id":"https://openalex.org/W2293318356","doi":"https://doi.org/10.1145/2847263.2847306","title":"t-QuadPlace","display_name":"t-QuadPlace","publication_year":2016,"publication_date":"2016-02-04","ids":{"openalex":"https://openalex.org/W2293318356","doi":"https://doi.org/10.1145/2847263.2847306","mag":"2293318356"},"language":"en","primary_location":{"id":"doi:10.1145/2847263.2847306","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2847263.2847306","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5080301072","display_name":"Nimish Agashiwala","orcid":null},"institutions":[{"id":"https://openalex.org/I130238516","display_name":"University of Minnesota","ror":"https://ror.org/017zqws13","country_code":"US","type":"education","lineage":["https://openalex.org/I130238516"]},{"id":"https://openalex.org/I4210101327","display_name":"Twin Cities Orthopedics","ror":"https://ror.org/01en4s460","country_code":"US","type":"healthcare","lineage":["https://openalex.org/I4210101327"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Nimish Agashiwala","raw_affiliation_strings":["University of Minnesota Twin Cities, Minneapolis, MN, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Minnesota Twin Cities, Minneapolis, MN, USA","institution_ids":["https://openalex.org/I4210101327","https://openalex.org/I130238516"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052798715","display_name":"Satya Prakash Upadhyay","orcid":null},"institutions":[{"id":"https://openalex.org/I130238516","display_name":"University of Minnesota","ror":"https://ror.org/017zqws13","country_code":"US","type":"education","lineage":["https://openalex.org/I130238516"]},{"id":"https://openalex.org/I4210101327","display_name":"Twin Cities Orthopedics","ror":"https://ror.org/01en4s460","country_code":"US","type":"healthcare","lineage":["https://openalex.org/I4210101327"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Satya Prakash Upadhyay","raw_affiliation_strings":["University of Minnesota Twin Cities, Minneapolis, MN, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Minnesota Twin Cities, Minneapolis, MN, USA","institution_ids":["https://openalex.org/I4210101327","https://openalex.org/I130238516"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5013257804","display_name":"Kia Bazargan","orcid":"https://orcid.org/0000-0003-3624-7366"},"institutions":[{"id":"https://openalex.org/I130238516","display_name":"University of Minnesota","ror":"https://ror.org/017zqws13","country_code":"US","type":"education","lineage":["https://openalex.org/I130238516"]},{"id":"https://openalex.org/I4210101327","display_name":"Twin Cities Orthopedics","ror":"https://ror.org/01en4s460","country_code":"US","type":"healthcare","lineage":["https://openalex.org/I4210101327"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kia Bazargan","raw_affiliation_strings":["University of Minnesota Twin Cities, Minneapolis, MN, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Minnesota Twin Cities, Minneapolis, MN, USA","institution_ids":["https://openalex.org/I4210101327","https://openalex.org/I130238516"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.00679139,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"284","last_page":"284"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7600436210632324},{"id":"https://openalex.org/keywords/placement","display_name":"Placement","score":0.7070931196212769},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.680791974067688},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6071118712425232},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.5968409776687622},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.5897770524024963},{"id":"https://openalex.org/keywords/critical-path-method","display_name":"Critical path method","score":0.5372872352600098},{"id":"https://openalex.org/keywords/simulated-annealing","display_name":"Simulated annealing","score":0.5192694664001465},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5142040252685547},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.465574711561203},{"id":"https://openalex.org/keywords/floorplan","display_name":"Floorplan","score":0.4540387988090515},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.42453569173812866},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3847651779651642},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3375150263309479},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2484668493270874},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.2109445035457611},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.19818022847175598},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.10736694931983948}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7600436210632324},{"id":"https://openalex.org/C117690923","wikidata":"https://www.wikidata.org/wiki/Q1484784","display_name":"Placement","level":4,"score":0.7070931196212769},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.680791974067688},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6071118712425232},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.5968409776687622},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.5897770524024963},{"id":"https://openalex.org/C115874739","wikidata":"https://www.wikidata.org/wiki/Q825377","display_name":"Critical path method","level":2,"score":0.5372872352600098},{"id":"https://openalex.org/C126980161","wikidata":"https://www.wikidata.org/wiki/Q863783","display_name":"Simulated annealing","level":2,"score":0.5192694664001465},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5142040252685547},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.465574711561203},{"id":"https://openalex.org/C130145326","wikidata":"https://www.wikidata.org/wiki/Q1553985","display_name":"Floorplan","level":2,"score":0.4540387988090515},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.42453569173812866},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3847651779651642},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3375150263309479},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2484668493270874},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.2109445035457611},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.19818022847175598},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.10736694931983948},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2847263.2847306","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2847263.2847306","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.5099999904632568,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":24,"referenced_works":["https://openalex.org/W1516835811","https://openalex.org/W1523051745","https://openalex.org/W1984954427","https://openalex.org/W1986026297","https://openalex.org/W2030852227","https://openalex.org/W2075137913","https://openalex.org/W2094806828","https://openalex.org/W2100502052","https://openalex.org/W2105565203","https://openalex.org/W2108411416","https://openalex.org/W2117793659","https://openalex.org/W2121244114","https://openalex.org/W2123094965","https://openalex.org/W2131333217","https://openalex.org/W2138206217","https://openalex.org/W2138383740","https://openalex.org/W2139637699","https://openalex.org/W2154014710","https://openalex.org/W2154302973","https://openalex.org/W2158961316","https://openalex.org/W2163763728","https://openalex.org/W4234223235","https://openalex.org/W6631410163","https://openalex.org/W6680484343"],"related_works":["https://openalex.org/W4256007160","https://openalex.org/W2094042791","https://openalex.org/W3153286430","https://openalex.org/W4205135025","https://openalex.org/W3015761757","https://openalex.org/W96081925","https://openalex.org/W2102616729","https://openalex.org/W1535529518","https://openalex.org/W2117901445","https://openalex.org/W2064910292"],"abstract_inverted_index":{"Conventional":[0],"Simulated":[1],"Annealing":[2],"(SA)":[3],"based":[4,93],"placement":[5,37,62,67,80,163,188,215],"methods":[6,35],"for":[7,36,68,75,116,195],"FPGAs":[8,69],"generate":[9],"high":[10,24],"quality":[11],"results":[12,108,207],"in":[13,44,168],"terms":[14],"of":[15,29,42,136],"wirelength":[16,87,140],"and":[17,56,88,141],"critical":[18,103,130],"path":[19,104,131],"delay,":[20],"but":[21],"at":[22,65,133],"a":[23,39,54,112],"runtime":[25,43,114,153,173],"cost.":[26],"In":[27,49],"case":[28],"modern":[30,225],"multi-million":[31],"gate":[32],"FPGAs,":[33],"SA-based":[34],"take":[38],"large":[40,199],"portion":[41],"the":[45,98,102,128,158,180,186,198],"FPGA":[46,227],"CAD":[47],"flow.":[48],"this":[50,210],"paper,":[51],"we":[52,178],"propose":[53],"fast":[55],"efficient":[57],"timing":[58,95],"driven":[59],"open-source":[60],"analytical":[61],"engine":[63,81,164],"targeted":[64],"global":[66,79,119,162,214],"followed":[70],"by":[71],"low":[72],"temperature":[73],"SA":[74],"detailed":[76,187],"placement.":[77],"Our":[78],"uses":[82],"quadratic":[83],"programming":[84],"to":[85,100,122,174,182],"minimize":[86,101],"employs":[89],"dynamic":[90],"net":[91],"weights":[92],"on":[94,110],"criticality":[96],"between":[97],"nets":[99],"delay":[105,132],"iteratively.":[106],"Experimental":[107],"show,":[109],"average,":[111],"30%":[113],"improvement":[115,154],"our":[117,161,172,190],"proposed":[118,191],"placer":[120,124,211],"compared":[121],"VPR":[123],"while":[125],"having":[126,201],"approximately":[127],"same":[129],"an":[134],"expense":[135],"3%":[137],"larger":[138],"overall":[139],"channel":[142],"width":[143],"after":[144],"routing":[145],"with":[146,224],"20":[147],"largest":[148],"MCNC":[149],"benchmark":[150],"circuits.":[151],"The":[152,206],"is":[155,165,221],"seen":[156],"despite":[157],"fact":[159],"that":[160,209],"currently":[166],"implemented":[167],"MATLAB.":[169],"We":[170],"expect":[171],"improve":[175],"notably":[176],"once":[177],"port":[179],"code":[181],"C.":[183],"On":[184],"combining":[185],"runtime,":[189],"approach":[192],"performs":[193,212],"faster":[194,213],"almost":[196],"all":[197,217],"circuits":[200],"more":[202],"than":[203],"250":[204],"blocks.":[205],"show":[208],"across":[216],"benchmarks,":[218],"hence":[219],"it":[220],"easily":[222],"scalable":[223],"complex":[226],"designs.":[228]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2016-06-24T00:00:00"}