{"id":"https://openalex.org/W2295385329","doi":"https://doi.org/10.1145/2847263.2847285","title":"HyperPipelining of High-Speed Interface Logic","display_name":"HyperPipelining of High-Speed Interface Logic","publication_year":2016,"publication_date":"2016-02-04","ids":{"openalex":"https://openalex.org/W2295385329","doi":"https://doi.org/10.1145/2847263.2847285","mag":"2295385329"},"language":"en","primary_location":{"id":"doi:10.1145/2847263.2847285","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2847263.2847285","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5067241056","display_name":"Gregg Baeckler","orcid":null},"institutions":[{"id":"https://openalex.org/I22433950","display_name":"Altera (United States)","ror":"https://ror.org/017b7j426","country_code":"US","type":"company","lineage":["https://openalex.org/I22433950"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Gregg Baeckler","raw_affiliation_strings":["Altera Corporation, San Jose, CA, USA"],"affiliations":[{"raw_affiliation_string":"Altera Corporation, San Jose, CA, USA","institution_ids":["https://openalex.org/I22433950"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5067241056"],"corresponding_institution_ids":["https://openalex.org/I22433950"],"apc_list":null,"apc_paid":null,"fwci":0.5791,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.69764407,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"2","last_page":"2"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/datapath","display_name":"Datapath","score":0.9517508745193481},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.7774026393890381},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7371106743812561},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6869446039199829},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5233629941940308},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5118104815483093},{"id":"https://openalex.org/keywords/ethernet","display_name":"Ethernet","score":0.4864046573638916},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.46779686212539673},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.4597679674625397},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4133700728416443},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.40102171897888184},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3883495628833771},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.36748817563056946},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.20162296295166016}],"concepts":[{"id":"https://openalex.org/C2781198647","wikidata":"https://www.wikidata.org/wiki/Q1633673","display_name":"Datapath","level":2,"score":0.9517508745193481},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.7774026393890381},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7371106743812561},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6869446039199829},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5233629941940308},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5118104815483093},{"id":"https://openalex.org/C172173386","wikidata":"https://www.wikidata.org/wiki/Q79984","display_name":"Ethernet","level":2,"score":0.4864046573638916},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.46779686212539673},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.4597679674625397},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4133700728416443},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.40102171897888184},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3883495628833771},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.36748817563056946},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.20162296295166016},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2847263.2847285","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2847263.2847285","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":1,"referenced_works":["https://openalex.org/W2264331490"],"related_works":["https://openalex.org/W2119748374","https://openalex.org/W2114514951","https://openalex.org/W1972393920","https://openalex.org/W1996820488","https://openalex.org/W2098419840","https://openalex.org/W1966764473","https://openalex.org/W2789349722","https://openalex.org/W1985308002","https://openalex.org/W2614722573","https://openalex.org/W2121963733"],"abstract_inverted_index":{"The":[0],"throughput":[1,34],"needs":[2,23],"of":[3,52],"networking":[4],"designs":[5,54],"on":[6],"FPGAs":[7],"are":[8],"constantly":[9],"growing":[10],"--":[11,55],"from":[12],"40Gbps":[13],"to":[14,24,31,43,48,58,84],"100Gbps,":[15],"400Gbps":[16],"and":[17,61],"beyond.":[18],"A":[19],"400G":[20],"Ethernet":[21],"MAC":[22],"process":[25],"wide":[26],"data":[27],"at":[28,87,95],"high":[29],"speeds":[30],"meet":[32],"the":[33,44,64],"needs.":[35],"Altera":[36],"recently":[37],"introduced":[38],"HyperFlexTM":[39],"[1][2][3],":[40],"a":[41,91,99],"change":[42],"fabric":[45],"architecture":[46],"aimed":[47],"facilitate":[49],"massive":[50],"pipelining":[51],"FPGA":[53],"allowing":[56],"them":[57],"run":[59],"faster":[60],"hence":[62],"alleviate":[63],"congestion":[65,104],"that":[66],"is":[67,105],"caused":[68],"by":[69],"widening":[70],"datapaths":[71],"beyond":[72],"512b":[73],"or":[74],"1024b.":[75],"Though":[76],"it":[77,80],"seems":[78],"counterintuitive":[79],"can":[81],"be":[82],"easier":[83],"close":[85],"timing":[86],"781":[88],"MHz":[89,97],"for":[90,98],"640b":[92],"datapath":[93,101],"than":[94],"390":[96],"1280b":[100],"when":[102],"wire":[103],"taken":[106],"into":[107],"account.":[108]},"counts_by_year":[{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
