{"id":"https://openalex.org/W2277819611","doi":"https://doi.org/10.1145/2847263.2847279","title":"Stratix\u2122 10 High Performance Routable Clock Networks","display_name":"Stratix\u2122 10 High Performance Routable Clock Networks","publication_year":2016,"publication_date":"2016-02-04","ids":{"openalex":"https://openalex.org/W2277819611","doi":"https://doi.org/10.1145/2847263.2847279","mag":"2277819611"},"language":"en","primary_location":{"id":"doi:10.1145/2847263.2847279","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2847263.2847279","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5032101034","display_name":"Carl Ebeling","orcid":"https://orcid.org/0000-0001-5032-3615"},"institutions":[{"id":"https://openalex.org/I22433950","display_name":"Altera (United States)","ror":"https://ror.org/017b7j426","country_code":"US","type":"company","lineage":["https://openalex.org/I22433950"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Carl Ebeling","raw_affiliation_strings":["Altera Corporation, San Jose, CA, USA"],"affiliations":[{"raw_affiliation_string":"Altera Corporation, San Jose, CA, USA","institution_ids":["https://openalex.org/I22433950"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031787837","display_name":"Dana How","orcid":"https://orcid.org/0000-0003-2843-1972"},"institutions":[{"id":"https://openalex.org/I22433950","display_name":"Altera (United States)","ror":"https://ror.org/017b7j426","country_code":"US","type":"company","lineage":["https://openalex.org/I22433950"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Dana How","raw_affiliation_strings":["Altera Corporation, San Jose, CA, USA"],"affiliations":[{"raw_affiliation_string":"Altera Corporation, San Jose, CA, USA","institution_ids":["https://openalex.org/I22433950"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102968798","display_name":"David Lewis","orcid":"https://orcid.org/0000-0002-8126-5662"},"institutions":[{"id":"https://openalex.org/I22433950","display_name":"Altera (United States)","ror":"https://ror.org/017b7j426","country_code":"US","type":"company","lineage":["https://openalex.org/I22433950"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"David Lewis","raw_affiliation_strings":["Altera Corporation, San Jose, CA, USA"],"affiliations":[{"raw_affiliation_string":"Altera Corporation, San Jose, CA, USA","institution_ids":["https://openalex.org/I22433950"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5078387900","display_name":"Herman Schmit","orcid":"https://orcid.org/0000-0002-0109-7604"},"institutions":[{"id":"https://openalex.org/I22433950","display_name":"Altera (United States)","ror":"https://ror.org/017b7j426","country_code":"US","type":"company","lineage":["https://openalex.org/I22433950"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Herman Schmit","raw_affiliation_strings":["Altera Corporation, San Jose, CA, USA"],"affiliations":[{"raw_affiliation_string":"Altera Corporation, San Jose, CA, USA","institution_ids":["https://openalex.org/I22433950"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5032101034"],"corresponding_institution_ids":["https://openalex.org/I22433950"],"apc_list":null,"apc_paid":null,"fwci":1.1026,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":{"value":0.79399823,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"64","last_page":"73"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.8668978214263916},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.76524418592453},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.7374389171600342},{"id":"https://openalex.org/keywords/cpu-multiplier","display_name":"CPU multiplier","score":0.7188261151313782},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.6724104881286621},{"id":"https://openalex.org/keywords/clock-network","display_name":"Clock network","score":0.6714217662811279},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6242132186889648},{"id":"https://openalex.org/keywords/clock-synchronization","display_name":"Clock synchronization","score":0.5785263180732727},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5683131217956543},{"id":"https://openalex.org/keywords/vector-clock","display_name":"Vector clock","score":0.5411481261253357},{"id":"https://openalex.org/keywords/timing-failure","display_name":"Timing failure","score":0.5142461657524109},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.513545036315918},{"id":"https://openalex.org/keywords/stratix","display_name":"Stratix","score":0.5008721351623535},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4883108139038086},{"id":"https://openalex.org/keywords/clock-drift","display_name":"Clock drift","score":0.4710507392883301},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.4507357180118561},{"id":"https://openalex.org/keywords/master-clock","display_name":"Master clock","score":0.43569308519363403},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.2496212124824524},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.24583041667938232},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.2127620279788971},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.12357720732688904},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07139769196510315}],"concepts":[{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.8668978214263916},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.76524418592453},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.7374389171600342},{"id":"https://openalex.org/C125576049","wikidata":"https://www.wikidata.org/wiki/Q2246273","display_name":"CPU multiplier","level":5,"score":0.7188261151313782},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.6724104881286621},{"id":"https://openalex.org/C2778182565","wikidata":"https://www.wikidata.org/wiki/Q1752879","display_name":"Clock network","level":5,"score":0.6714217662811279},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6242132186889648},{"id":"https://openalex.org/C129891060","wikidata":"https://www.wikidata.org/wiki/Q1513059","display_name":"Clock synchronization","level":4,"score":0.5785263180732727},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5683131217956543},{"id":"https://openalex.org/C52563298","wikidata":"https://www.wikidata.org/wiki/Q1413349","display_name":"Vector clock","level":5,"score":0.5411481261253357},{"id":"https://openalex.org/C104654189","wikidata":"https://www.wikidata.org/wiki/Q7806740","display_name":"Timing failure","level":5,"score":0.5142461657524109},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.513545036315918},{"id":"https://openalex.org/C2776277307","wikidata":"https://www.wikidata.org/wiki/Q22074755","display_name":"Stratix","level":3,"score":0.5008721351623535},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4883108139038086},{"id":"https://openalex.org/C155837451","wikidata":"https://www.wikidata.org/wiki/Q1069144","display_name":"Clock drift","level":5,"score":0.4710507392883301},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.4507357180118561},{"id":"https://openalex.org/C65595194","wikidata":"https://www.wikidata.org/wiki/Q1000863","display_name":"Master clock","level":4,"score":0.43569308519363403},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.2496212124824524},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.24583041667938232},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.2127620279788971},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.12357720732688904},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07139769196510315},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2847263.2847279","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2847263.2847279","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1965195759","https://openalex.org/W2011778848","https://openalex.org/W2049960281","https://openalex.org/W2069460396","https://openalex.org/W2107547422","https://openalex.org/W2111515250","https://openalex.org/W2113128433","https://openalex.org/W2118482092","https://openalex.org/W2139637699","https://openalex.org/W2142395333","https://openalex.org/W2217863744","https://openalex.org/W2478848959","https://openalex.org/W3150149142"],"related_works":["https://openalex.org/W3093058274","https://openalex.org/W4247180033","https://openalex.org/W2617666058","https://openalex.org/W1596690381","https://openalex.org/W2033989103","https://openalex.org/W2096283348","https://openalex.org/W4200015704","https://openalex.org/W2148462217","https://openalex.org/W2787237207","https://openalex.org/W2277819611"],"abstract_inverted_index":{"We":[0,24,49,83],"present":[1],"the":[2,6,17,26,47,69,73,92,96],"clock":[3,13,19,32,38,57,65,77,89,93,105],"architecture":[4],"of":[5,21,76,95,104],"Stratix?10":[7],"FPGA,":[8],"which":[9],"uses":[10],"a":[11,87],"routable":[12,31,88],"network":[14,33],"rather":[15],"than":[16],"fixed":[18],"networks":[20],"previous":[22],"generations.":[23],"describe":[25],"flexibility":[27],"provided":[28],"by":[29,100],"this":[30,52],"and":[34,43],"how":[35,51,86],"arbitrarily":[36],"sized":[37],"trees":[39,58],"can":[40,59],"be":[41],"synthesized":[42],"placed":[44],"anywhere":[45],"on":[46],"FPGA.":[48],"show":[50],"capability":[53],"to":[54,71,102],"generate":[55],"customized":[56],"provide":[60],"better":[61],"performance":[62],"through":[63],"reduced":[64],"loss":[66,94],"while":[67],"maintaining":[68],"ability":[70],"handle":[72],"large":[74],"number":[75],"domains":[78],"that":[79],"modern":[80],"systems":[81],"require.":[82],"experimentally":[84],"demonstrate":[85],"tree":[90],"reduces":[91],"user":[97],"design":[98],"implementation":[99],"up":[101],"6%":[103],"insertion":[106],"delay.":[107]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":2},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
