{"id":"https://openalex.org/W1974307224","doi":"https://doi.org/10.1145/2818950.2818952","title":"Near Data Processing","display_name":"Near Data Processing","publication_year":2015,"publication_date":"2015-10-05","ids":{"openalex":"https://openalex.org/W1974307224","doi":"https://doi.org/10.1145/2818950.2818952","mag":"1974307224"},"language":"en","primary_location":{"id":"doi:10.1145/2818950.2818952","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2818950.2818952","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2015 International Symposium on Memory Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5051612984","display_name":"Syed Minhaj Hassan","orcid":null},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Syed Minhaj Hassan","raw_affiliation_strings":["School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, Georgia","[School of Electrical and Computer Engineering Georgia, Institute of Technology Atlanta, Georgia]"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, Georgia","institution_ids":["https://openalex.org/I130701444"]},{"raw_affiliation_string":"[School of Electrical and Computer Engineering Georgia, Institute of Technology Atlanta, Georgia]","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111855694","display_name":"Sudhakar Yalamanchili","orcid":null},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sudhakar Yalamanchili","raw_affiliation_strings":["School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, Georgia","[School of Electrical and Computer Engineering Georgia, Institute of Technology Atlanta, Georgia]"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, Georgia","institution_ids":["https://openalex.org/I130701444"]},{"raw_affiliation_string":"[School of Electrical and Computer Engineering Georgia, Institute of Technology Atlanta, Georgia]","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5009591041","display_name":"Saibal Mukhopadhyay","orcid":"https://orcid.org/0000-0002-8894-3390"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Saibal Mukhopadhyay","raw_affiliation_strings":["School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, Georgia","[School of Electrical and Computer Engineering Georgia, Institute of Technology Atlanta, Georgia]"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, Georgia","institution_ids":["https://openalex.org/I130701444"]},{"raw_affiliation_string":"[School of Electrical and Computer Engineering Georgia, Institute of Technology Atlanta, Georgia]","institution_ids":["https://openalex.org/I130701444"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5051612984"],"corresponding_institution_ids":["https://openalex.org/I130701444"],"apc_list":null,"apc_paid":null,"fwci":1.9969,"has_fulltext":false,"cited_by_count":30,"citation_normalized_percentile":{"value":0.87837098,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"11","last_page":"21"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8325139284133911},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.638116717338562},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.5669302940368652},{"id":"https://openalex.org/keywords/cas-latency","display_name":"CAS latency","score":0.5487648844718933},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.5401611924171448},{"id":"https://openalex.org/keywords/memory-hierarchy","display_name":"Memory hierarchy","score":0.5239203572273254},{"id":"https://openalex.org/keywords/universal-memory","display_name":"Universal memory","score":0.50240159034729},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.4718860387802124},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.4478866457939148},{"id":"https://openalex.org/keywords/registered-memory","display_name":"Registered memory","score":0.4470590353012085},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.44313251972198486},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.4146571755409241},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.41376790404319763},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4065251052379608},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.37460771203041077},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.31123220920562744},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.2675490379333496},{"id":"https://openalex.org/keywords/overlay","display_name":"Overlay","score":0.2598685622215271},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.253390371799469},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.18225377798080444},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.17662039399147034}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8325139284133911},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.638116717338562},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.5669302940368652},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.5487648844718933},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.5401611924171448},{"id":"https://openalex.org/C2778100165","wikidata":"https://www.wikidata.org/wiki/Q1589327","display_name":"Memory hierarchy","level":3,"score":0.5239203572273254},{"id":"https://openalex.org/C195053848","wikidata":"https://www.wikidata.org/wiki/Q7894141","display_name":"Universal memory","level":5,"score":0.50240159034729},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.4718860387802124},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.4478866457939148},{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.4470590353012085},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.44313251972198486},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.4146571755409241},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.41376790404319763},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4065251052379608},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.37460771203041077},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.31123220920562744},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.2675490379333496},{"id":"https://openalex.org/C136085584","wikidata":"https://www.wikidata.org/wiki/Q910289","display_name":"Overlay","level":2,"score":0.2598685622215271},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.253390371799469},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.18225377798080444},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.17662039399147034},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2818950.2818952","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2818950.2818952","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2015 International Symposium on Memory Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G6366902396","display_name":null,"funder_award_id":"0855110","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"}],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"},{"id":"https://openalex.org/F4320306087","display_name":"Semiconductor Research Corporation","ror":"https://ror.org/047z4n946"},{"id":"https://openalex.org/F4320338291","display_name":"Sandia National Laboratories","ror":"https://ror.org/01apwpt12"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W1501077214","https://openalex.org/W1975237352","https://openalex.org/W1975698617","https://openalex.org/W1976186353","https://openalex.org/W1985431949","https://openalex.org/W1994562616","https://openalex.org/W2013626513","https://openalex.org/W2032281090","https://openalex.org/W2061587924","https://openalex.org/W2067155801","https://openalex.org/W2069756028","https://openalex.org/W2082982763","https://openalex.org/W2090678868","https://openalex.org/W2118668706","https://openalex.org/W2122636510","https://openalex.org/W2131413854","https://openalex.org/W2162639668","https://openalex.org/W2177765591","https://openalex.org/W2573662600","https://openalex.org/W4256463526","https://openalex.org/W6658708280"],"related_works":["https://openalex.org/W3008068282","https://openalex.org/W2138825797","https://openalex.org/W4243618206","https://openalex.org/W2564569739","https://openalex.org/W2148966412","https://openalex.org/W1975444747","https://openalex.org/W1971441083","https://openalex.org/W1210553197","https://openalex.org/W175601589","https://openalex.org/W2020261724"],"abstract_inverted_index":{"A":[0],"promising":[1],"recent":[2],"development":[3],"that":[4,60,145],"can":[5,65,152],"provide":[6],"continued":[7],"scaling":[8],"of":[9,51,63,76,133],"performance":[10,155],"is":[11],"the":[12,27,30,34,48,71,88,101,110,115,120,131],"ability":[13],"to":[14,123],"stack":[15],"multiple":[16],"DRAM":[17,91],"layers":[18],"on":[19,43,100,114],"a":[20,52,124,146],"multi-core":[21],"processor":[22],"die.":[23],"This":[24,78],"paper":[25],"analyzes":[26],"interaction":[28],"between":[29],"interconnection":[31,102],"network":[32],"and":[33,40,58,112,128,137],"memory":[35,72,81,121,150],"hierarchy":[36,122],"in":[37,86],"such":[38],"systems,":[39],"its":[41],"impact":[42],"system":[44,54,151],"performance.":[45],"We":[46],"explore":[47,130],"design":[49],"considerations":[50],"3D":[53,64,149],"with":[55,73],"DRAM-on-processor":[56],"stacking":[57],"note":[59],"full":[61],"advantages":[62],"only":[66],"be":[67],"achieved":[68],"by":[69,156],"configuring":[70],"high":[74],"number":[75],"channels.":[77],"significantly":[79],"increases":[80],"level":[82],"parallelism":[83],"which":[84],"results":[85,143],"decreasing":[87],"traffic":[89,113],"per":[90],"bank,":[92],"reducing":[93],"their":[94],"queuing":[95],"delays,":[96],"but":[97],"increasing":[98],"it":[99],"network,":[103,116],"making":[104],"remote":[105],"accesses":[106],"expensive.":[107],"To":[108],"reduce":[109],"latency":[111],"we":[117],"propose":[118],"restructuring":[119],"memory-side":[125],"cache":[126],"organization":[127],"also":[129],"effects":[132],"various":[134],"address":[135],"translations":[136],"OS":[138],"page":[139],"allocation":[140],"strategies.":[141],"Our":[142],"indicate":[144],"carefully":[147],"designed":[148],"already":[153],"improve":[154],"25-35%":[157],"without":[158],"looking":[159],"towards":[160],"new":[161],"sophisticated":[162],"techniques.":[163]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":4},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":13},{"year":2018,"cited_by_count":4},{"year":2017,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
