{"id":"https://openalex.org/W2088634313","doi":"https://doi.org/10.1145/2786980","title":"Leveraging Transactional Execution for Memory Consistency Model Emulation","display_name":"Leveraging Transactional Execution for Memory Consistency Model Emulation","publication_year":2015,"publication_date":"2015-08-31","ids":{"openalex":"https://openalex.org/W2088634313","doi":"https://doi.org/10.1145/2786980","mag":"2088634313"},"language":"en","primary_location":{"id":"doi:10.1145/2786980","is_oa":true,"landing_page_url":"https://doi.org/10.1145/2786980","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/2786980","source":{"id":"https://openalex.org/S26056741","display_name":"ACM Transactions on Architecture and Code Optimization","issn_l":"1544-3566","issn":["1544-3566","1544-3973"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Architecture and Code Optimization","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"bronze","oa_url":"https://dl.acm.org/doi/pdf/10.1145/2786980","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5103563776","display_name":"Ragavendra Natarajan","orcid":null},"institutions":[{"id":"https://openalex.org/I130238516","display_name":"University of Minnesota","ror":"https://ror.org/017zqws13","country_code":"US","type":"education","lineage":["https://openalex.org/I130238516"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Ragavendra Natarajan","raw_affiliation_strings":["University of Minnesota, Keller Hall, Minneapolis MN"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Minnesota, Keller Hall, Minneapolis MN","institution_ids":["https://openalex.org/I130238516"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5053597061","display_name":"Antonia Zhai","orcid":"https://orcid.org/0000-0002-8921-1415"},"institutions":[{"id":"https://openalex.org/I130238516","display_name":"University of Minnesota","ror":"https://ror.org/017zqws13","country_code":"US","type":"education","lineage":["https://openalex.org/I130238516"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Antonia Zhai","raw_affiliation_strings":["University of Minnesota, Keller Hall, Minneapolis MN"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Minnesota, Keller Hall, Minneapolis MN","institution_ids":["https://openalex.org/I130238516"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5103563776"],"corresponding_institution_ids":["https://openalex.org/I130238516"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":true,"cited_by_count":1,"citation_normalized_percentile":{"value":0.08179306,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"12","issue":"3","first_page":"1","last_page":"24"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10772","display_name":"Distributed systems and fault tolerance","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8746722936630249},{"id":"https://openalex.org/keywords/emulation","display_name":"Emulation","score":0.7444803714752197},{"id":"https://openalex.org/keywords/transactional-memory","display_name":"Transactional memory","score":0.6303358674049377},{"id":"https://openalex.org/keywords/consistency-model","display_name":"Consistency model","score":0.588860034942627},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.4983487129211426},{"id":"https://openalex.org/keywords/cache-coherence","display_name":"Cache coherence","score":0.4799628257751465},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.47013455629348755},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.4537220299243927},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.43728744983673096},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.42999914288520813},{"id":"https://openalex.org/keywords/consistency","display_name":"Consistency (knowledge bases)","score":0.42051106691360474},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.21692314743995667},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.19729411602020264},{"id":"https://openalex.org/keywords/database-transaction","display_name":"Database transaction","score":0.17601490020751953},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.1538856029510498},{"id":"https://openalex.org/keywords/data-consistency","display_name":"Data consistency","score":0.10108789801597595}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8746722936630249},{"id":"https://openalex.org/C149810388","wikidata":"https://www.wikidata.org/wiki/Q5374873","display_name":"Emulation","level":2,"score":0.7444803714752197},{"id":"https://openalex.org/C134277064","wikidata":"https://www.wikidata.org/wiki/Q878206","display_name":"Transactional memory","level":3,"score":0.6303358674049377},{"id":"https://openalex.org/C37279795","wikidata":"https://www.wikidata.org/wiki/Q2492305","display_name":"Consistency model","level":3,"score":0.588860034942627},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.4983487129211426},{"id":"https://openalex.org/C141917322","wikidata":"https://www.wikidata.org/wiki/Q1025017","display_name":"Cache coherence","level":5,"score":0.4799628257751465},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.47013455629348755},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.4537220299243927},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.43728744983673096},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.42999914288520813},{"id":"https://openalex.org/C2776436953","wikidata":"https://www.wikidata.org/wiki/Q5163215","display_name":"Consistency (knowledge bases)","level":2,"score":0.42051106691360474},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.21692314743995667},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.19729411602020264},{"id":"https://openalex.org/C75949130","wikidata":"https://www.wikidata.org/wiki/Q848010","display_name":"Database transaction","level":2,"score":0.17601490020751953},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.1538856029510498},{"id":"https://openalex.org/C93361087","wikidata":"https://www.wikidata.org/wiki/Q4426698","display_name":"Data consistency","level":2,"score":0.10108789801597595},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C50522688","wikidata":"https://www.wikidata.org/wiki/Q189833","display_name":"Economic growth","level":1,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2786980","is_oa":true,"landing_page_url":"https://doi.org/10.1145/2786980","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/2786980","source":{"id":"https://openalex.org/S26056741","display_name":"ACM Transactions on Architecture and Code Optimization","issn_l":"1544-3566","issn":["1544-3566","1544-3973"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Architecture and Code Optimization","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1145/2786980","is_oa":true,"landing_page_url":"https://doi.org/10.1145/2786980","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/2786980","source":{"id":"https://openalex.org/S26056741","display_name":"ACM Transactions on Architecture and Code Optimization","issn_l":"1544-3566","issn":["1544-3566","1544-3973"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Architecture and Code Optimization","raw_type":"journal-article"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2088634313.pdf","grobid_xml":"https://content.openalex.org/works/W2088634313.grobid-xml"},"referenced_works_count":31,"referenced_works":["https://openalex.org/W75086091","https://openalex.org/W151922429","https://openalex.org/W1522250664","https://openalex.org/W1525350307","https://openalex.org/W1789713128","https://openalex.org/W2014791196","https://openalex.org/W2029601347","https://openalex.org/W2032945467","https://openalex.org/W2036267700","https://openalex.org/W2036548030","https://openalex.org/W2039509099","https://openalex.org/W2054739713","https://openalex.org/W2058317042","https://openalex.org/W2072389180","https://openalex.org/W2087476542","https://openalex.org/W2096343842","https://openalex.org/W2099661831","https://openalex.org/W2100373446","https://openalex.org/W2105900173","https://openalex.org/W2120635877","https://openalex.org/W2123322769","https://openalex.org/W2127591346","https://openalex.org/W2145021036","https://openalex.org/W2158947256","https://openalex.org/W2159582805","https://openalex.org/W2160781056","https://openalex.org/W2161935172","https://openalex.org/W2165199599","https://openalex.org/W2169000705","https://openalex.org/W2169875292","https://openalex.org/W4244282989"],"related_works":["https://openalex.org/W1606808321","https://openalex.org/W2108871581","https://openalex.org/W1569520790","https://openalex.org/W2460246254","https://openalex.org/W2093234962","https://openalex.org/W2519290774","https://openalex.org/W1991421251","https://openalex.org/W1557295419","https://openalex.org/W1598877338","https://openalex.org/W2088634313"],"abstract_inverted_index":{"System":[0,25],"emulation":[1,26,40,78,87,96,278,302],"is":[2,69,91,324,330,339,372],"widely":[3],"used":[4],"in":[5,85,174,225,334],"today\u2019s":[6],"computer":[7],"systems.":[8],"This":[9],"technology":[10],"opens":[11],"new":[12,58],"opportunities":[13],"for":[14,145,254,274,332,389,400],"resource":[15],"sharing":[16],"as":[17,19],"well":[18],"enhancing":[20],"system":[21,77,110,153],"security":[22],"and":[23,51,63,100,264,272,319,361,382,392,397],"reliability.":[24],"across":[27],"different":[28],"instruction":[29],"set":[30],"architectures":[31],"(ISA)":[32],"can":[33,41,167,188,351],"enable":[34,42],"further":[35],"opportunities.":[36],"For":[37],"example,":[38],"cross-ISA":[39,86,109],"workload":[43],"consolidation":[44],"over":[45],"a":[46,155,292],"wide":[47],"range":[48],"of":[49,57,95,125,193,211,286],"microprocessors":[50,204],"potentially":[52],"facilitate":[53],"the":[54,73,93,98,101,123,137,151,162,165,175,180,191,194,212,220,234,243,248,266,280,308,316,320,336,359,362,368,376,383],"seamless":[55],"deployment":[56],"processor":[59],"architectures.":[60],"As":[61],"multicore":[62,89],"manycore":[64],"processors":[65],"become":[66],"pervasive,":[67],"it":[68],"important":[70],"to":[71,118,135,161,178,238,314,349,374],"address":[72,136],"challenges":[74],"toward":[75],"supporting":[76],"on":[79,88,201,233,242,279,291,358],"these":[80,288],"platforms.":[81],"A":[82,341],"key":[83],"challenge":[84],"systems":[90],"ensuring":[92],"correctness":[94],"when":[97,307],"guest":[99,163,181,256],"host":[102,152,235,244],"memory":[103,146,157,169,182,186,230,257,275,299,328],"consistency":[104,147,158,217,276,300],"models":[105],"differ.":[106],"Many":[107],"existing":[108],"emulators":[111,132],"are":[112,116,133,311],"sequential,":[113],"thus":[114],"they":[115,141],"able":[117,134,373],"avoid":[119],"this":[120,260],"problem":[121],"at":[122,171,219],"cost":[124],"significant":[126],"performance":[127,138,192],"degradation.":[128],"Recently":[129],"proposed":[130,369],"parallel":[131,294],"limitation;":[139],"however,":[140],"provide":[142],"limited":[143],"support":[144,199],"model":[148,159,277,301],"emulation.":[149],"When":[150],"has":[154],"weaker":[156],"compared":[160],"system,":[164],"emulator":[166],"insert":[168],"fences":[170,187,273,329],"appropriate":[172],"locations":[173],"translated":[176,195,213],"code":[177,214],"enforce":[179],"ordering":[183],"constraints.":[184],"These":[185],"significantly":[189],"degrade":[190],"code.":[196],"Transactional":[197,209],"execution":[198,210,250,385],"available":[200],"certain":[202],"recent":[203],"provides":[205],"an":[206],"alternative":[207],"approach.":[208],"enforces":[215],"sequential":[216],"(SC)":[218],"coarse-grained":[221],"transaction":[222,309,317,321,337],"level,":[223],"which":[224,335,347],"turn":[226],"ensures":[227],"that":[228,247,298,344,367],"all":[229],"accesses":[231],"made":[232],"machine":[236,245],"conform":[237],"SC.":[239],"Enforcing":[240],"SC":[241],"guarantees":[246],"emulated":[249],"will":[251],"be":[252],"correct":[253],"any":[255],"model.":[258],"In":[259],"article,":[261],"we":[262],"compare":[263],"evaluate":[265],"overheads":[267],"associated":[268],"with":[269],"using":[270,303],"transactions":[271,304],"Intel":[281],"Haswell":[282],"processor.":[283],"Our":[284,355],"experience":[285],"implementing":[287],"two":[289],"approaches":[290],"state-of-the-art":[293],"emulator,":[295],"COREMU,":[296],"demonstrates":[297],"performs":[305],"better":[306,331],"sizes":[310],"large":[312],"enough":[313],"amortize":[315],"overhead":[318,338],"conflict":[322],"rate":[323],"low,":[325],"whereas":[326],"inserting":[327],"applications":[333],"high.":[340],"hybrid":[342,370],"implementation":[343],"dynamically":[345],"determines":[346],"approach":[348,371,386],"invoke":[350],"outperform":[352,375,393],"both":[353],"approaches.":[354],"results,":[356],"based":[357],"SPLASH-2":[360],"PARSEC":[363],"benchmark":[364],"suites,":[365],"demonstrate":[366],"fence":[377],"insertion":[378],"mechanism":[379],"by":[380,387,395],"4.9%":[381],"transactional":[384],"24.9%":[388],"two-thread":[390],"applications,":[391],"them":[394],"4.5%":[396],"44.7%,":[398],"respectively,":[399],"four-threaded":[401],"execution.":[402]},"counts_by_year":[{"year":2020,"cited_by_count":1}],"updated_date":"2026-05-21T06:26:12.895304","created_date":"2025-10-10T00:00:00"}