{"id":"https://openalex.org/W2105808347","doi":"https://doi.org/10.1145/2765491.2765503","title":"Process/design co-optimization of regular logic tiles for double-gate silicon nanowire transistors","display_name":"Process/design co-optimization of regular logic tiles for double-gate silicon nanowire transistors","publication_year":2012,"publication_date":"2012-07-04","ids":{"openalex":"https://openalex.org/W2105808347","doi":"https://doi.org/10.1145/2765491.2765503","mag":"2105808347"},"language":"en","primary_location":{"id":"doi:10.1145/2765491.2765503","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2765491.2765503","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"http://infoscience.epfl.ch/record/179923","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5111926197","display_name":"Shashikanth Bobba","orcid":null},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":true,"raw_author_name":"Shashikanth Bobba","raw_affiliation_strings":["LSI, EPFL, Lausanne, Switzerland","LSI, EPFL, Lausanne, Switzerland#TAB#"],"affiliations":[{"raw_affiliation_string":"LSI, EPFL, Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]},{"raw_affiliation_string":"LSI, EPFL, Lausanne, Switzerland#TAB#","institution_ids":["https://openalex.org/I5124864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5002568331","display_name":"Pierre\u2010Emmanuel Gaillardon","orcid":"https://orcid.org/0000-0003-3634-3999"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Pierre-Emmanuel Gaillardon","raw_affiliation_strings":["LSI, EPFL, Lausanne, Switzerland","LSI, EPFL, Lausanne, Switzerland#TAB#"],"affiliations":[{"raw_affiliation_string":"LSI, EPFL, Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]},{"raw_affiliation_string":"LSI, EPFL, Lausanne, Switzerland#TAB#","institution_ids":["https://openalex.org/I5124864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100409898","display_name":"Jian Zhang","orcid":"https://orcid.org/0000-0001-8711-0058"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Jian Zhang","raw_affiliation_strings":["LSI, EPFL, Lausanne, Switzerland","LSI, EPFL, Lausanne, Switzerland#TAB#"],"affiliations":[{"raw_affiliation_string":"LSI, EPFL, Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]},{"raw_affiliation_string":"LSI, EPFL, Lausanne, Switzerland#TAB#","institution_ids":["https://openalex.org/I5124864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5068047109","display_name":"Michele De Marchi","orcid":"https://orcid.org/0000-0001-7967-6983"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Michele De Marchi","raw_affiliation_strings":["LSI, EPFL, Lausanne, Switzerland","LSI, EPFL, Lausanne, Switzerland#TAB#"],"affiliations":[{"raw_affiliation_string":"LSI, EPFL, Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]},{"raw_affiliation_string":"LSI, EPFL, Lausanne, Switzerland#TAB#","institution_ids":["https://openalex.org/I5124864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5055710356","display_name":"Davide Sacchetto","orcid":null},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Davide Sacchetto","raw_affiliation_strings":["LSM, EPFL, Lausanne, Switzerland","[LSM, EPFL, Lausanne, Switzerland]"],"affiliations":[{"raw_affiliation_string":"LSM, EPFL, Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]},{"raw_affiliation_string":"[LSM, EPFL, Lausanne, Switzerland]","institution_ids":["https://openalex.org/I5124864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5072423303","display_name":"Yusuf Leblebici","orcid":null},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Yusuf Leblebici","raw_affiliation_strings":["LSM, EPFL, Lausanne, Switzerland","[LSM, EPFL, Lausanne, Switzerland]"],"affiliations":[{"raw_affiliation_string":"LSM, EPFL, Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]},{"raw_affiliation_string":"[LSM, EPFL, Lausanne, Switzerland]","institution_ids":["https://openalex.org/I5124864"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5072927296","display_name":"Giovanni De Micheli","orcid":"https://orcid.org/0000-0002-7827-3215"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Giovanni De Micheli","raw_affiliation_strings":["LSI, EPFL, Lausanne, Switzerland","LSI, EPFL, Lausanne, Switzerland#TAB#"],"affiliations":[{"raw_affiliation_string":"LSI, EPFL, Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]},{"raw_affiliation_string":"LSI, EPFL, Lausanne, Switzerland#TAB#","institution_ids":["https://openalex.org/I5124864"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":7,"corresponding_author_ids":["https://openalex.org/A5111926197"],"corresponding_institution_ids":["https://openalex.org/I5124864"],"apc_list":null,"apc_paid":null,"fwci":1.2483,"has_fulltext":false,"cited_by_count":17,"citation_normalized_percentile":{"value":0.82362617,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"55","last_page":"60"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11272","display_name":"Nanowire Synthesis and Applications","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/nanowire","display_name":"Nanowire","score":0.7020000219345093},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.6363425254821777},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.6221638917922974},{"id":"https://openalex.org/keywords/silicon-nanowires","display_name":"Silicon nanowires","score":0.5930736064910889},{"id":"https://openalex.org/keywords/silicon","display_name":"Silicon","score":0.5567787289619446},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5480735898017883},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.497456818819046},{"id":"https://openalex.org/keywords/optoelectronics","display_name":"Optoelectronics","score":0.42511802911758423},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.38753461837768555},{"id":"https://openalex.org/keywords/nanotechnology","display_name":"Nanotechnology","score":0.33919399976730347},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.3338475823402405},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2995462417602539},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19608718156814575},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.0709277093410492}],"concepts":[{"id":"https://openalex.org/C74214498","wikidata":"https://www.wikidata.org/wiki/Q631739","display_name":"Nanowire","level":2,"score":0.7020000219345093},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.6363425254821777},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.6221638917922974},{"id":"https://openalex.org/C2986665194","wikidata":"https://www.wikidata.org/wiki/Q28324872","display_name":"Silicon nanowires","level":3,"score":0.5930736064910889},{"id":"https://openalex.org/C544956773","wikidata":"https://www.wikidata.org/wiki/Q670","display_name":"Silicon","level":2,"score":0.5567787289619446},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5480735898017883},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.497456818819046},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.42511802911758423},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.38753461837768555},{"id":"https://openalex.org/C171250308","wikidata":"https://www.wikidata.org/wiki/Q11468","display_name":"Nanotechnology","level":1,"score":0.33919399976730347},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.3338475823402405},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2995462417602539},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19608718156814575},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0709277093410492},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1145/2765491.2765503","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2765491.2765503","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.259.5442","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.259.5442","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://infoscience.epfl.ch/record/179923/files/114.pdf","raw_type":"text"},{"id":"pmh:oai:infoscience.epfl.ch:179923","is_oa":true,"landing_page_url":"http://infoscience.epfl.ch/record/179923","pdf_url":null,"source":{"id":"https://openalex.org/S4306400487","display_name":"Infoscience (Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Text"}],"best_oa_location":{"id":"pmh:oai:infoscience.epfl.ch:179923","is_oa":true,"landing_page_url":"http://infoscience.epfl.ch/record/179923","pdf_url":null,"source":{"id":"https://openalex.org/S4306400487","display_name":"Infoscience (Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Text"},"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.6000000238418579}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1880528517","https://openalex.org/W1971495518","https://openalex.org/W1997965855","https://openalex.org/W1998339330","https://openalex.org/W2035368095","https://openalex.org/W2047241543","https://openalex.org/W2069814353","https://openalex.org/W2101656799","https://openalex.org/W2109887272","https://openalex.org/W2112314900","https://openalex.org/W2117181658","https://openalex.org/W2135818056","https://openalex.org/W2138876803","https://openalex.org/W2155211950","https://openalex.org/W2156694126","https://openalex.org/W2540448892","https://openalex.org/W2542085131"],"related_works":["https://openalex.org/W3143516596","https://openalex.org/W2089372549","https://openalex.org/W1669133231","https://openalex.org/W4300780679","https://openalex.org/W2033291290","https://openalex.org/W134694013","https://openalex.org/W2014118584","https://openalex.org/W2089236473","https://openalex.org/W2080553548","https://openalex.org/W2588941787"],"abstract_inverted_index":{"Ambipolar":[0],"transistors":[1,49],"with":[2,66],"on-line":[3],"configurability":[4],"to":[5,72,112],"n-type":[6],"and":[7,105],"p-type":[8],"polarity":[9],"are":[10,70],"desirable":[11],"for":[12,27,39,43],"future":[13],"integrated":[14],"circuits.":[15],"Regular":[16],"logic":[17,41],"tiles":[18,42],"have":[19],"been":[20],"recognized":[21],"as":[22],"an":[23,84],"efficient":[24],"layout":[25],"fabric":[26],"ambipolar":[28],"devices.":[29],"In":[30],"this":[31],"work,":[32],"we":[33,93],"present":[34],"a":[35],"process/design":[36],"co-optimization":[37],"approach":[38],"designing":[40],"double-gate":[44],"silicon":[45],"nanowire":[46],"field":[47],"effect":[48],"(DG-SiNWFET)":[50],"technology.":[51],"A":[52],"compact":[53],"Verilog-A":[54],"model":[55],"of":[56,76,89],"the":[57,74,102],"device":[58],"is":[59],"extracted":[60],"from":[61],"TCAD":[62],"simulations.":[63],"Cell":[64],"libraries":[65],"different":[67],"tile":[68,86],"configurations":[69],"mapped":[71],"study":[73],"performance":[75],"DG-SiNWFET":[77],"technology":[78,81],"at":[79],"various":[80],"nodes.":[82],"With":[83],"optimal":[85],"size":[87],"comprising":[88],"6":[90],"vertically-stacked":[91],"nanowires,":[92],"observe":[94],"1.6x":[95],"improvement":[96,107],"in":[97,101,108],"area,":[98],"2x":[99],"decrease":[100],"leakage":[103],"power":[104],"1.8x":[106],"delay":[109],"when":[110],"compared":[111],"Si-CMOS.":[113]},"counts_by_year":[{"year":2024,"cited_by_count":2},{"year":2022,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":4},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":4}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}
