{"id":"https://openalex.org/W1993183930","doi":"https://doi.org/10.1145/2744769.2744910","title":"Sequential equivalence checking of clock-gated circuits","display_name":"Sequential equivalence checking of clock-gated circuits","publication_year":2015,"publication_date":"2015-06-02","ids":{"openalex":"https://openalex.org/W1993183930","doi":"https://doi.org/10.1145/2744769.2744910","mag":"1993183930"},"language":"en","primary_location":{"id":"doi:10.1145/2744769.2744910","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2744769.2744910","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 52nd Annual Design Automation Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5028440275","display_name":"Yu-Yun Dai","orcid":"https://orcid.org/0000-0001-8058-0380"},"institutions":[{"id":"https://openalex.org/I95457486","display_name":"University of California, Berkeley","ror":"https://ror.org/01an7q238","country_code":"US","type":"education","lineage":["https://openalex.org/I95457486"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Yu-Yun Dai","raw_affiliation_strings":["University of California, Berkeley","Department of EECS, University of California, Berkeley, U.S.A"],"affiliations":[{"raw_affiliation_string":"University of California, Berkeley","institution_ids":["https://openalex.org/I95457486"]},{"raw_affiliation_string":"Department of EECS, University of California, Berkeley, U.S.A","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5113693870","display_name":"Kei-Yong Khoo","orcid":null},"institutions":[{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kei-Yong Khoo","raw_affiliation_strings":["Cadence Design Systems Inc., San Jose","[Cadence Design Systems, Inc., San Jose, U.S.A.]"],"affiliations":[{"raw_affiliation_string":"Cadence Design Systems Inc., San Jose","institution_ids":["https://openalex.org/I66217453"]},{"raw_affiliation_string":"[Cadence Design Systems, Inc., San Jose, U.S.A.]","institution_ids":["https://openalex.org/I66217453"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5064568178","display_name":"Robert K. Brayton","orcid":"https://orcid.org/0000-0002-3861-1718"},"institutions":[{"id":"https://openalex.org/I95457486","display_name":"University of California, Berkeley","ror":"https://ror.org/01an7q238","country_code":"US","type":"education","lineage":["https://openalex.org/I95457486"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Robert K. Brayton","raw_affiliation_strings":["University of California, Berkeley","Department of EECS, University of California, Berkeley, U.S.A"],"affiliations":[{"raw_affiliation_string":"University of California, Berkeley","institution_ids":["https://openalex.org/I95457486"]},{"raw_affiliation_string":"Department of EECS, University of California, Berkeley, U.S.A","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5028440275"],"corresponding_institution_ids":["https://openalex.org/I95457486"],"apc_list":null,"apc_paid":null,"fwci":0.3946,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.66356981,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9951000213623047,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/equivalence","display_name":"Equivalence (formal languages)","score":0.6616238355636597},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6567012667655945},{"id":"https://openalex.org/keywords/formal-equivalence-checking","display_name":"Formal equivalence checking","score":0.633330762386322},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.6182637810707092},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.5906385183334351},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.5454627871513367},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.519413948059082},{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.5073530077934265},{"id":"https://openalex.org/keywords/gating","display_name":"Gating","score":0.4301314651966095},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.42622482776641846},{"id":"https://openalex.org/keywords/formal-verification","display_name":"Formal verification","score":0.33788591623306274},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.32214581966400146},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.2833414077758789},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.27287524938583374},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.26387572288513184},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.2509733736515045},{"id":"https://openalex.org/keywords/discrete-mathematics","display_name":"Discrete mathematics","score":0.11297357082366943},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.07471302151679993}],"concepts":[{"id":"https://openalex.org/C2780069185","wikidata":"https://www.wikidata.org/wiki/Q7977945","display_name":"Equivalence (formal languages)","level":2,"score":0.6616238355636597},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6567012667655945},{"id":"https://openalex.org/C96654402","wikidata":"https://www.wikidata.org/wiki/Q5469962","display_name":"Formal equivalence checking","level":3,"score":0.633330762386322},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.6182637810707092},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.5906385183334351},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.5454627871513367},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.519413948059082},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.5073530077934265},{"id":"https://openalex.org/C194544171","wikidata":"https://www.wikidata.org/wiki/Q21105679","display_name":"Gating","level":2,"score":0.4301314651966095},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.42622482776641846},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.33788591623306274},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.32214581966400146},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.2833414077758789},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.27287524938583374},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.26387572288513184},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.2509733736515045},{"id":"https://openalex.org/C118615104","wikidata":"https://www.wikidata.org/wiki/Q121416","display_name":"Discrete mathematics","level":1,"score":0.11297357082366943},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.07471302151679993},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0},{"id":"https://openalex.org/C42407357","wikidata":"https://www.wikidata.org/wiki/Q521","display_name":"Physiology","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2744769.2744910","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2744769.2744910","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 52nd Annual Design Automation Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"},{"id":"https://openalex.org/F4320306087","display_name":"Semiconductor Research Corporation","ror":"https://ror.org/047z4n946"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W359341721","https://openalex.org/W1495266209","https://openalex.org/W1528837436","https://openalex.org/W1819209966","https://openalex.org/W1915669309","https://openalex.org/W1973665222","https://openalex.org/W1980023055","https://openalex.org/W2081719483","https://openalex.org/W2099994752","https://openalex.org/W2118791871","https://openalex.org/W2137564865","https://openalex.org/W2500165681"],"related_works":["https://openalex.org/W2355703891","https://openalex.org/W2164310930","https://openalex.org/W4230644986","https://openalex.org/W2099994752","https://openalex.org/W1989756446","https://openalex.org/W2183548685","https://openalex.org/W2048768419","https://openalex.org/W2124398226","https://openalex.org/W2163532979","https://openalex.org/W2043111827"],"abstract_inverted_index":{"Sequential":[0],"clock-gating":[1,20,55],"can":[2],"lead":[3,74],"to":[4,10,25,51,75,102],"easier":[5],"equivalence":[6,14,32,36],"checking":[7,15],"problems,":[8],"compared":[9],"the":[11,38,45,71,86],"general":[12],"sequential":[13,19,35,62],"(SEC)":[16],"problem.":[17],"Modern":[18],"techniques":[21],"introduce":[22],"control":[23],"structures":[24],"disable":[26],"unnecessary":[27],"clocking.":[28],"This":[29],"violates":[30],"combinational":[31],"but":[33],"maintains":[34],"between":[37],"original":[39],"and":[40,67,98],"revised":[41],"circuits.":[42,82],"We":[43],"propose":[44],"use":[46],"of":[47,70,96],"characteristic":[48],"graphs":[49],"(CGs)":[50],"extract":[52],"essential":[53],"LTL":[54],"properties,":[56],"which":[57],"when":[58,100],"proved":[59],"imply":[60],"certain":[61],"redundancies.":[63],"The":[64],"extraction,":[65],"proof":[66],"subsequent":[68],"removal":[69],"implied":[72],"redundancies":[73],"an":[76],"efficient":[77],"SEC":[78,88],"procedure":[79,89],"for":[80],"clock-gated":[81],"Experiments":[83],"show":[84],"that":[85],"proposed":[87],"substantially":[90],"outperforms":[91],"existing":[92],"methods":[93],"in":[94],"terms":[95],"speed":[97],"scalability":[99],"applied":[101],"several":[103],"difficult":[104],"cases.":[105]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}