{"id":"https://openalex.org/W1980040075","doi":"https://doi.org/10.1145/2744769.2744893","title":"Physically aware high level synthesis design flow","display_name":"Physically aware high level synthesis design flow","publication_year":2015,"publication_date":"2015-06-02","ids":{"openalex":"https://openalex.org/W1980040075","doi":"https://doi.org/10.1145/2744769.2744893","mag":"1980040075"},"language":"en","primary_location":{"id":"doi:10.1145/2744769.2744893","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2744769.2744893","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 52nd Annual Design Automation Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5027591708","display_name":"Tatsuoka Masato","orcid":null},"institutions":[{"id":"https://openalex.org/I2800638042","display_name":"Socionext (Japan)","ror":"https://ror.org/04ma89d43","country_code":"JP","type":"company","lineage":["https://openalex.org/I2800638042"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Masato Tatsuoka","raw_affiliation_strings":["Socionext, Inc","Socionext, Inc., Japan"],"affiliations":[{"raw_affiliation_string":"Socionext, Inc","institution_ids":[]},{"raw_affiliation_string":"Socionext, Inc., Japan","institution_ids":["https://openalex.org/I2800638042"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5065944593","display_name":"Watanabe Ryosuke","orcid":null},"institutions":[{"id":"https://openalex.org/I2800638042","display_name":"Socionext (Japan)","ror":"https://ror.org/04ma89d43","country_code":"JP","type":"company","lineage":["https://openalex.org/I2800638042"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Ryosuke Watanabe","raw_affiliation_strings":["Socionext, Inc","Socionext, Inc., Japan"],"affiliations":[{"raw_affiliation_string":"Socionext, Inc","institution_ids":[]},{"raw_affiliation_string":"Socionext, Inc., Japan","institution_ids":["https://openalex.org/I2800638042"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5028184583","display_name":"Tatsushi Otsuka","orcid":null},"institutions":[{"id":"https://openalex.org/I2800638042","display_name":"Socionext (Japan)","ror":"https://ror.org/04ma89d43","country_code":"JP","type":"company","lineage":["https://openalex.org/I2800638042"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Tatsushi Otsuka","raw_affiliation_strings":["Socionext, Inc","Socionext, Inc., Japan"],"affiliations":[{"raw_affiliation_string":"Socionext, Inc","institution_ids":[]},{"raw_affiliation_string":"Socionext, Inc., Japan","institution_ids":["https://openalex.org/I2800638042"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5090477551","display_name":"Takashi Hasegawa","orcid":"https://orcid.org/0000-0003-0147-506X"},"institutions":[{"id":"https://openalex.org/I2800638042","display_name":"Socionext (Japan)","ror":"https://ror.org/04ma89d43","country_code":"JP","type":"company","lineage":["https://openalex.org/I2800638042"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Takashi Hasegawa","raw_affiliation_strings":["Socionext, Inc","Socionext, Inc., Japan"],"affiliations":[{"raw_affiliation_string":"Socionext, Inc","institution_ids":[]},{"raw_affiliation_string":"Socionext, Inc., Japan","institution_ids":["https://openalex.org/I2800638042"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103136845","display_name":"Qiang Zhu","orcid":"https://orcid.org/0000-0001-7094-9236"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Qiang Zhu","raw_affiliation_strings":["Cadence Design Systems, Japan"],"affiliations":[{"raw_affiliation_string":"Cadence Design Systems, Japan","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111560689","display_name":"Ryosuke Okamura","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Ryosuke Okamura","raw_affiliation_strings":["Cadence Design Systems, Japan"],"affiliations":[{"raw_affiliation_string":"Cadence Design Systems, Japan","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5069180252","display_name":"Xingri Li","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Xingri Li","raw_affiliation_strings":["Cadence Design Systems, Japan"],"affiliations":[{"raw_affiliation_string":"Cadence Design Systems, Japan","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5082486393","display_name":"Tsuyoshi Takabatake","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Tsuyoshi Takabatake","raw_affiliation_strings":["Cadence Design Systems, Japan"],"affiliations":[{"raw_affiliation_string":"Cadence Design Systems, Japan","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":8,"corresponding_author_ids":["https://openalex.org/A5027591708"],"corresponding_institution_ids":["https://openalex.org/I2800638042"],"apc_list":null,"apc_paid":null,"fwci":0.9689,"has_fulltext":false,"cited_by_count":15,"citation_normalized_percentile":{"value":0.75191493,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/systemc","display_name":"SystemC","score":0.832687258720398},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.8242650032043457},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7576919794082642},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.6748970150947571},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5829958319664001},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5255966186523438},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.47579798102378845},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4373074173927307},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3941501975059509},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.39028114080429077},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.24074023962020874},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.21128469705581665},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.1947489082813263}],"concepts":[{"id":"https://openalex.org/C2776928060","wikidata":"https://www.wikidata.org/wiki/Q1753563","display_name":"SystemC","level":2,"score":0.832687258720398},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.8242650032043457},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7576919794082642},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.6748970150947571},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5829958319664001},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5255966186523438},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.47579798102378845},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4373074173927307},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3941501975059509},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.39028114080429077},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.24074023962020874},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.21128469705581665},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.1947489082813263},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2744769.2744893","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2744769.2744893","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 52nd Annual Design Automation Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W2033863865","https://openalex.org/W2047631674","https://openalex.org/W2072400712","https://openalex.org/W2097099414","https://openalex.org/W2107980957","https://openalex.org/W2121993820","https://openalex.org/W2127680764","https://openalex.org/W2132814771","https://openalex.org/W2135117148","https://openalex.org/W2146241631"],"related_works":["https://openalex.org/W2752828786","https://openalex.org/W2242433395","https://openalex.org/W1603163876","https://openalex.org/W2133642747","https://openalex.org/W2543290882","https://openalex.org/W2118796996","https://openalex.org/W3147061323","https://openalex.org/W2227166741","https://openalex.org/W2365114398","https://openalex.org/W2097806352"],"abstract_inverted_index":{"High":[0],"Level":[1],"Synthesis":[2],"(HLS)":[3],"has":[4],"many":[5],"productivity":[6],"advantages":[7],"over":[8],"traditional":[9],"RTL":[10],"design,":[11],"but":[12,107],"routing":[13,105],"congestion":[14,54,75,106],"is":[15],"difficult":[16],"to":[17,20,61,72,79,88],"resolve":[18,73],"due":[19],"the":[21,65,74,80],"lack":[22],"of":[23,64],"physical":[24],"information":[25],"in":[26],"HLS.":[27],"In":[28],"this":[29,49,86,98],"paper":[30],"we":[31],"propose":[32],"a":[33,39,89],"novel":[34],"design":[35,82,93,108],"flow":[36,87,99],"by":[37],"integrating":[38],"HLS":[40,91],"tool":[41],"with":[42,94],"physically":[43],"aware":[44],"logic":[45],"synthesis":[46],"technology.":[47],"Using":[48],"approach,":[50],"one":[51],"can":[52,100],"discover":[53],"problems":[55,76],"early":[56],"and":[57,110],"trace":[58],"their":[59],"sources":[60],"specific":[62],"parts":[63],"input":[66],"SystemC":[67],"models.":[68],"This":[69],"allows":[70],"designers":[71],"before":[77],"going":[78],"layout":[81],"phase.":[83],"We":[84],"applied":[85],"large-scale":[90],"production":[92],"results":[95],"showing":[96],"that":[97],"significantly":[101],"improve":[102],"not":[103],"only":[104],"area":[109],"timing":[111],"as":[112],"well.":[113]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":2},{"year":2016,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
