{"id":"https://openalex.org/W2089877521","doi":"https://doi.org/10.1145/2744769.2744802","title":"Avoiding transitional effects in dynamic circuit specialisation on FPGAs","display_name":"Avoiding transitional effects in dynamic circuit specialisation on FPGAs","publication_year":2015,"publication_date":"2015-06-02","ids":{"openalex":"https://openalex.org/W2089877521","doi":"https://doi.org/10.1145/2744769.2744802","mag":"2089877521"},"language":"en","primary_location":{"id":"doi:10.1145/2744769.2744802","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2744769.2744802","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 52nd Annual Design Automation Conference","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5020622964","display_name":"Karel Heyse","orcid":null},"institutions":[{"id":"https://openalex.org/I32597200","display_name":"Ghent University","ror":"https://ror.org/00cv9y106","country_code":"BE","type":"education","lineage":["https://openalex.org/I32597200"]}],"countries":["BE"],"is_corresponding":false,"raw_author_name":"Karel Heyse","raw_affiliation_strings":["Ghent University, Gent, Belgium","Ghent University, Sint-Pietersnieuwstraat 41, Gent, Belgium"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Ghent University, Gent, Belgium","institution_ids":["https://openalex.org/I32597200"]},{"raw_affiliation_string":"Ghent University, Sint-Pietersnieuwstraat 41, Gent, Belgium","institution_ids":["https://openalex.org/I32597200"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5004502321","display_name":"Dirk Stroobandt","orcid":"https://orcid.org/0000-0002-4477-5313"},"institutions":[{"id":"https://openalex.org/I32597200","display_name":"Ghent University","ror":"https://ror.org/00cv9y106","country_code":"BE","type":"education","lineage":["https://openalex.org/I32597200"]}],"countries":["BE"],"is_corresponding":false,"raw_author_name":"Dirk Stroobandt","raw_affiliation_strings":["Ghent University, Gent, Belgium","Ghent University, Sint-Pietersnieuwstraat 41, Gent, Belgium"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Ghent University, Gent, Belgium","institution_ids":["https://openalex.org/I32597200"]},{"raw_affiliation_string":"Ghent University, Sint-Pietersnieuwstraat 41, Gent, Belgium","institution_ids":["https://openalex.org/I32597200"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I32597200"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/reconfigurability","display_name":"Reconfigurability","score":0.9496320486068726},{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.8238240480422974},{"id":"https://openalex.org/keywords/downtime","display_name":"Downtime","score":0.779508113861084},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7259845733642578},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.638994574546814},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5442401170730591},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.14172741770744324}],"concepts":[{"id":"https://openalex.org/C2780149590","wikidata":"https://www.wikidata.org/wiki/Q7302742","display_name":"Reconfigurability","level":2,"score":0.9496320486068726},{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.8238240480422974},{"id":"https://openalex.org/C180591934","wikidata":"https://www.wikidata.org/wiki/Q1253369","display_name":"Downtime","level":2,"score":0.779508113861084},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7259845733642578},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.638994574546814},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5442401170730591},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.14172741770744324}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/2744769.2744802","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2744769.2744802","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 52nd Annual Design Automation Conference","raw_type":"proceedings-article"},{"id":"pmh:oai:archive.ugent.be:6838698","is_oa":false,"landing_page_url":"http://hdl.handle.net/1854/LU-6838698","pdf_url":null,"source":{"id":"https://openalex.org/S4306400478","display_name":"Ghent University Academic Bibliography (Ghent University)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I32597200","host_organization_name":"Ghent University","host_organization_lineage":["https://openalex.org/I32597200"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"ISBN: 9781450335201","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W4072037","https://openalex.org/W1585183574","https://openalex.org/W1801332854","https://openalex.org/W2015780963","https://openalex.org/W2038213124","https://openalex.org/W2048944807","https://openalex.org/W2085828379","https://openalex.org/W2124766622","https://openalex.org/W2151872233","https://openalex.org/W2160565804"],"related_works":["https://openalex.org/W2152623100","https://openalex.org/W2096417281","https://openalex.org/W25204318","https://openalex.org/W2077035242","https://openalex.org/W2138895528","https://openalex.org/W3042643149","https://openalex.org/W1999203047","https://openalex.org/W3201977823","https://openalex.org/W2362203107","https://openalex.org/W2084703527"],"abstract_inverted_index":{"Dynamic":[0],"Circuit":[1],"Specialisation":[2],"(DCS)":[3],"is":[4,52],"a":[5,16,77],"technique":[6],"that":[7,34,67],"uses":[8],"the":[9,44,57],"reconfigurability":[10],"of":[11,42,59,79],"an":[12,36],"FPGA":[13],"to":[14],"optimise":[15],"circuit":[17,46],"during":[18],"run-time,":[19],"thus":[20],"achieving":[21],"higher":[22],"performance":[23],"and":[24,64],"lower":[25],"resource":[26],"cost.":[27],"However,":[28],"run-time":[29],"reconfiguration":[30],"causes":[31],"transitional":[32],"effects":[33],"form":[35],"important":[37],"problem":[38],"for":[39,61],"DCS.":[40],"Because":[41],"these,":[43],"DCS":[45,60],"cannot":[47,68],"be":[48],"used":[49],"while":[50],"it":[51],"being":[53],"reconfigured.":[54],"This":[55],"limits":[56],"usability":[58],"streaming":[62],"applications":[63,66],"other":[65,72],"tolerate":[69],"downtime.":[70],"For":[71],"applications,":[73],"this":[74],"results":[75],"in":[76],"loss":[78],"performance.":[80]},"counts_by_year":[{"year":2019,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}