{"id":"https://openalex.org/W1973994521","doi":"https://doi.org/10.1145/2744769.2744787","title":"A timing graph based approach to mode merging","display_name":"A timing graph based approach to mode merging","publication_year":2015,"publication_date":"2015-06-02","ids":{"openalex":"https://openalex.org/W1973994521","doi":"https://doi.org/10.1145/2744769.2744787","mag":"1973994521"},"language":"en","primary_location":{"id":"doi:10.1145/2744769.2744787","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2744769.2744787","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 52nd Annual Design Automation Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5011118886","display_name":"Subramanyam Sripada","orcid":null},"institutions":[{"id":"https://openalex.org/I4210088951","display_name":"Synopsys (United States)","ror":"https://ror.org/013by2m91","country_code":"US","type":"company","lineage":["https://openalex.org/I4210088951"]},{"id":"https://openalex.org/I1335490905","display_name":"Synopsys (Switzerland)","ror":"https://ror.org/03mb54f81","country_code":"CH","type":"company","lineage":["https://openalex.org/I1335490905","https://openalex.org/I4210088951"]}],"countries":["CH","US"],"is_corresponding":true,"raw_author_name":"Subramanyam Sripada","raw_affiliation_strings":["Synopsys Inc","Synopsys Inc.USA"],"affiliations":[{"raw_affiliation_string":"Synopsys Inc","institution_ids":["https://openalex.org/I1335490905"]},{"raw_affiliation_string":"Synopsys Inc.USA","institution_ids":["https://openalex.org/I4210088951"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5020675149","display_name":"Murthy Palla","orcid":null},"institutions":[{"id":"https://openalex.org/I1335490905","display_name":"Synopsys (Switzerland)","ror":"https://ror.org/03mb54f81","country_code":"CH","type":"company","lineage":["https://openalex.org/I1335490905","https://openalex.org/I4210088951"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Murthy Palla","raw_affiliation_strings":["Synopsys India Pvt. Ltd","Synopsys India Pvt. Ltd., USA"],"affiliations":[{"raw_affiliation_string":"Synopsys India Pvt. Ltd","institution_ids":[]},{"raw_affiliation_string":"Synopsys India Pvt. Ltd., USA","institution_ids":["https://openalex.org/I1335490905"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5011118886"],"corresponding_institution_ids":["https://openalex.org/I1335490905","https://openalex.org/I4210088951"],"apc_list":null,"apc_paid":null,"fwci":0.1973,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.57498555,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7800959348678589},{"id":"https://openalex.org/keywords/merge","display_name":"Merge (version control)","score":0.7674788236618042},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.503084123134613},{"id":"https://openalex.org/keywords/graph","display_name":"Graph","score":0.49267131090164185},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.4755237400531769},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.44944480061531067},{"id":"https://openalex.org/keywords/mode","display_name":"Mode (computer interface)","score":0.4406260550022125},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.3448057472705841},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.32354769110679626},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.26993900537490845},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.19392302632331848},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1571766436100006},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.15580034255981445}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7800959348678589},{"id":"https://openalex.org/C197129107","wikidata":"https://www.wikidata.org/wiki/Q1921621","display_name":"Merge (version control)","level":2,"score":0.7674788236618042},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.503084123134613},{"id":"https://openalex.org/C132525143","wikidata":"https://www.wikidata.org/wiki/Q141488","display_name":"Graph","level":2,"score":0.49267131090164185},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.4755237400531769},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.44944480061531067},{"id":"https://openalex.org/C48677424","wikidata":"https://www.wikidata.org/wiki/Q6888088","display_name":"Mode (computer interface)","level":2,"score":0.4406260550022125},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.3448057472705841},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.32354769110679626},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.26993900537490845},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.19392302632331848},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1571766436100006},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.15580034255981445},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2744769.2744787","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2744769.2744787","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 52nd Annual Design Automation Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.5899999737739563}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W1980951645","https://openalex.org/W2151547042","https://openalex.org/W2169671942","https://openalex.org/W2169751402","https://openalex.org/W4253360222"],"related_works":["https://openalex.org/W4234886518","https://openalex.org/W2389591058","https://openalex.org/W2382112581","https://openalex.org/W2014709025","https://openalex.org/W3124036233","https://openalex.org/W4229787472","https://openalex.org/W2155019192","https://openalex.org/W2486541857","https://openalex.org/W4388667102","https://openalex.org/W2080035745"],"abstract_inverted_index":{"With":[0],"shrinking":[1],"technologies":[2],"and":[3,20,23,27,143],"increasing":[4],"design":[5],"complexities,":[6],"it":[7],"is":[8,64,92,111,120,137],"common":[9],"to":[10,31,44,54,61,83,107,113],"have":[11],"a":[12,100],"large":[13,140],"number":[14,36,68],"of":[15,37,69,132],"modes":[16,70,74],"(functional,":[17],"scan,":[18],"test":[19],"so":[21],"on)":[22],"corners":[24],"(PVT":[25],"device":[26],"interconnect).":[28],"This":[29,135],"leads":[30],"an":[32,121],"explosion":[33],"in":[34],"the":[35,67,80,125,130,144],"scenarios":[38],"(#modes":[39],"\u00d7":[40],"#corners)":[41],"that":[42,110,124],"need":[43],"be":[45],"validated":[46],"for":[47],"timing.":[48],"While":[49],"multiple":[50],"tactics":[51],"are":[52,146],"required":[53],"handle":[55],"this":[56,63,96],"problem,":[57],"one":[58],"essential":[59],"way":[60],"address":[62],"by":[65,71],"reducing":[66],"merging":[72,88,109],"individual":[73],"into":[75],"superset":[76],"modes.":[77],"However,":[78],"with":[79,89],"overriding":[81],"necessity":[82],"maintain":[84],"sign-off":[85],"accuracy,":[86],"mode":[87,108],"high":[90],"merge-factor":[91],"very":[93],"complex.":[94],"In":[95],"paper,":[97],"we":[98],"propose":[99],"novel":[101],"automated":[102],"timing":[103],"graph":[104],"based":[105],"approach":[106],"designed":[112],"meet":[114],"these":[115],"requirements.":[116],"By":[117],"construction,":[118],"there":[119],"inbuilt":[122],"validation":[123],"merged":[126],"constraints":[127],"correctly":[128],"model":[129],"intent":[131],"original":[133],"constraints.":[134],"technology":[136],"tested":[138],"on":[139],"industrial":[141],"designs":[142],"results":[145],"provided.":[147]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
