{"id":"https://openalex.org/W1996258688","doi":"https://doi.org/10.1145/2742060.2742119","title":"Skew Bounded Buffer Tree Resynthesis For Clock Power Optimization","display_name":"Skew Bounded Buffer Tree Resynthesis For Clock Power Optimization","publication_year":2015,"publication_date":"2015-05-19","ids":{"openalex":"https://openalex.org/W1996258688","doi":"https://doi.org/10.1145/2742060.2742119","mag":"1996258688"},"language":"en","primary_location":{"id":"doi:10.1145/2742060.2742119","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2742060.2742119","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 25th edition on Great Lakes Symposium on VLSI","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101967869","display_name":"Subhendu Roy","orcid":"https://orcid.org/0000-0001-8554-563X"},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Subhendu Roy","raw_affiliation_strings":["The University of Texas at Austin, AUSTIN, TX, USA","The University of Texas At Austin, Austin, TX, USA"],"affiliations":[{"raw_affiliation_string":"The University of Texas at Austin, AUSTIN, TX, USA","institution_ids":["https://openalex.org/I86519309"]},{"raw_affiliation_string":"The University of Texas At Austin, Austin, TX, USA","institution_ids":["https://openalex.org/I86519309"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5011883763","display_name":"David Z. Pan","orcid":"https://orcid.org/0000-0002-5705-2501"},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"David Z. Pan","raw_affiliation_strings":["The University of Texas at Austin, AUSTIN, TX, USA","The University of Texas At Austin, Austin, TX, USA"],"affiliations":[{"raw_affiliation_string":"The University of Texas at Austin, AUSTIN, TX, USA","institution_ids":["https://openalex.org/I86519309"]},{"raw_affiliation_string":"The University of Texas At Austin, Austin, TX, USA","institution_ids":["https://openalex.org/I86519309"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5067917827","display_name":"Pavlos M. Mattheakis","orcid":null},"institutions":[{"id":"https://openalex.org/I105695857","display_name":"Siemens (Hungary)","ror":"https://ror.org/01rk7mv85","country_code":"HU","type":"company","lineage":["https://openalex.org/I105695857","https://openalex.org/I1325886976"]}],"countries":["HU"],"is_corresponding":false,"raw_author_name":"Pavlos M. Mattheakis","raw_affiliation_strings":["Mentor Graphics, Grenoble, France",", Mentor Graphics, Grenoble, France"],"affiliations":[{"raw_affiliation_string":"Mentor Graphics, Grenoble, France","institution_ids":[]},{"raw_affiliation_string":", Mentor Graphics, Grenoble, France","institution_ids":["https://openalex.org/I105695857"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5022039087","display_name":"Peter S. Colyer","orcid":null},"institutions":[{"id":"https://openalex.org/I4210156212","display_name":"Mentor Technologies","ror":"https://ror.org/05vewsj04","country_code":"US","type":"other","lineage":["https://openalex.org/I4210156212"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Peter S. Colyer","raw_affiliation_strings":["Mentor Graphics, Fremont, CA, USA","Mentor Graphics, Fremont, CA, USA#TAB#"],"affiliations":[{"raw_affiliation_string":"Mentor Graphics, Fremont, CA, USA","institution_ids":["https://openalex.org/I4210156212"]},{"raw_affiliation_string":"Mentor Graphics, Fremont, CA, USA#TAB#","institution_ids":["https://openalex.org/I4210156212"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5074123126","display_name":"Laurent Masse-Navette","orcid":null},"institutions":[{"id":"https://openalex.org/I105695857","display_name":"Siemens (Hungary)","ror":"https://ror.org/01rk7mv85","country_code":"HU","type":"company","lineage":["https://openalex.org/I105695857","https://openalex.org/I1325886976"]}],"countries":["HU"],"is_corresponding":false,"raw_author_name":"Laurent Masse-Navette","raw_affiliation_strings":["Mentor Graphics, Grenoble, France",", Mentor Graphics, Grenoble, France"],"affiliations":[{"raw_affiliation_string":"Mentor Graphics, Grenoble, France","institution_ids":[]},{"raw_affiliation_string":", Mentor Graphics, Grenoble, France","institution_ids":["https://openalex.org/I105695857"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5073743453","display_name":"Pierre-Olivier Ribet","orcid":null},"institutions":[{"id":"https://openalex.org/I105695857","display_name":"Siemens (Hungary)","ror":"https://ror.org/01rk7mv85","country_code":"HU","type":"company","lineage":["https://openalex.org/I105695857","https://openalex.org/I1325886976"]}],"countries":["HU"],"is_corresponding":false,"raw_author_name":"Pierre-Olivier Ribet","raw_affiliation_strings":["Mentor Graphics, Grenoble, France",", Mentor Graphics, Grenoble, France"],"affiliations":[{"raw_affiliation_string":"Mentor Graphics, Grenoble, France","institution_ids":[]},{"raw_affiliation_string":", Mentor Graphics, Grenoble, France","institution_ids":["https://openalex.org/I105695857"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5101967869"],"corresponding_institution_ids":["https://openalex.org/I86519309"],"apc_list":null,"apc_paid":null,"fwci":0.3946,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.66376963,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"87","last_page":"90"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.8661576509475708},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.7765055894851685},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.7189072370529175},{"id":"https://openalex.org/keywords/cpu-multiplier","display_name":"CPU multiplier","score":0.7031685709953308},{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.6695749759674072},{"id":"https://openalex.org/keywords/timing-failure","display_name":"Timing failure","score":0.6634373068809509},{"id":"https://openalex.org/keywords/clock-network","display_name":"Clock network","score":0.6177259087562561},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.591488242149353},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5593429207801819},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5099204778671265},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.43987658619880676},{"id":"https://openalex.org/keywords/dynamic-demand","display_name":"Dynamic demand","score":0.4131550192832947},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3466523289680481},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.33904117345809937},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.25561466813087463},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.12437763810157776},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.08776068687438965}],"concepts":[{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.8661576509475708},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.7765055894851685},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.7189072370529175},{"id":"https://openalex.org/C125576049","wikidata":"https://www.wikidata.org/wiki/Q2246273","display_name":"CPU multiplier","level":5,"score":0.7031685709953308},{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.6695749759674072},{"id":"https://openalex.org/C104654189","wikidata":"https://www.wikidata.org/wiki/Q7806740","display_name":"Timing failure","level":5,"score":0.6634373068809509},{"id":"https://openalex.org/C2778182565","wikidata":"https://www.wikidata.org/wiki/Q1752879","display_name":"Clock network","level":5,"score":0.6177259087562561},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.591488242149353},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5593429207801819},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5099204778671265},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.43987658619880676},{"id":"https://openalex.org/C45872418","wikidata":"https://www.wikidata.org/wiki/Q5318966","display_name":"Dynamic demand","level":3,"score":0.4131550192832947},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3466523289680481},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.33904117345809937},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.25561466813087463},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.12437763810157776},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.08776068687438965},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2742060.2742119","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2742060.2742119","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 25th edition on Great Lakes Symposium on VLSI","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":23,"referenced_works":["https://openalex.org/W1507707340","https://openalex.org/W1594033353","https://openalex.org/W1608654372","https://openalex.org/W1974610062","https://openalex.org/W1982784844","https://openalex.org/W2002848805","https://openalex.org/W2004375829","https://openalex.org/W2011778848","https://openalex.org/W2020480076","https://openalex.org/W2037865991","https://openalex.org/W2041950850","https://openalex.org/W2075885431","https://openalex.org/W2078299328","https://openalex.org/W2117616504","https://openalex.org/W2136047350","https://openalex.org/W2142850552","https://openalex.org/W2149417654","https://openalex.org/W2162112388","https://openalex.org/W2167708050","https://openalex.org/W2180955215","https://openalex.org/W4248399305","https://openalex.org/W6630243770","https://openalex.org/W6636331600"],"related_works":["https://openalex.org/W2088914741","https://openalex.org/W4247180033","https://openalex.org/W2559451387","https://openalex.org/W2617666058","https://openalex.org/W2803012234","https://openalex.org/W2090213929","https://openalex.org/W2165139624","https://openalex.org/W3006003651","https://openalex.org/W2127892766","https://openalex.org/W2144282137"],"abstract_inverted_index":{"With":[0],"aggressive":[1],"technology":[2],"scaling":[3],"in":[4,15,140,153],"nanometer":[5],"regime,":[6],"a":[7,63,93,150],"significant":[8],"fraction":[9],"of":[10,89,136],"dynamic":[11,146],"power":[12,147],"is":[13,42],"consumed":[14],"the":[16,50,76,87,90,154],"clock":[17,36,39,51,72,77,117,141,145,155],"network":[18,78],"due":[19],"to":[20,32,70],"its":[21,97],"high":[22],"switching":[23],"activity.":[24],"Clock":[25],"networks":[26,118],"are":[27],"typically":[28],"synthesized":[29,81,119],"and":[30,82,100,120,138,144],"routed":[31,121],"optimize":[33,71],"for":[34],"zero":[35],"skew.":[37,156],"However,":[38],"skew":[40,64,88],"optimization":[41],"often":[43],"accompanied":[44],"with":[45,116,149],"routing":[46],"overhead":[47,152],"which":[48],"increases":[49],"net":[52,73,142],"capacitance":[53,74,143],"thereby":[54],"consuming":[55],"more":[56],"power.":[57],"In":[58],"this":[59],"paper,":[60],"we":[61],"propose":[62],"bounded":[65],"buffer":[66],"tree":[67],"resynthesis":[68],"algorithm":[69,85],"after":[75],"has":[79],"been":[80],"routed.":[83],"Our":[84],"restricts":[86],"designs":[91],"within":[92],"specified":[94],"margin":[95],"from":[96],"original":[98],"skew,":[99],"does":[101],"not":[102],"introduce":[103],"any":[104],"additional":[105],"Design":[106],"Rule":[107],"Check":[108],"(DRC)":[109],"violation.":[110],"Experimental":[111],"results":[112],"on":[113],"industrial":[114,124],"designs,":[115],"by":[122],"an":[123,133],"tool,":[125],"have":[126],"demonstrated":[127],"that":[128],"our":[129],"approach":[130],"can":[131],"achieve":[132],"average":[134],"reduction":[135],"5.6%":[137],"3.5%":[139],"respectively":[148],"marginal":[151]},"counts_by_year":[{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
