{"id":"https://openalex.org/W2087723567","doi":"https://doi.org/10.1145/2742060.2742095","title":"A Novel Static D-Flip-Flop Topology for Low Swing Clocking","display_name":"A Novel Static D-Flip-Flop Topology for Low Swing Clocking","publication_year":2015,"publication_date":"2015-05-19","ids":{"openalex":"https://openalex.org/W2087723567","doi":"https://doi.org/10.1145/2742060.2742095","mag":"2087723567"},"language":"en","primary_location":{"id":"doi:10.1145/2742060.2742095","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2742060.2742095","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 25th edition on Great Lakes Symposium on VLSI","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5040915860","display_name":"Mallika Rathore","orcid":"https://orcid.org/0000-0002-3829-3887"},"institutions":[{"id":"https://openalex.org/I4210154351","display_name":"Marvell (United States)","ror":"https://ror.org/04wmff902","country_code":"US","type":"company","lineage":["https://openalex.org/I4210092679","https://openalex.org/I4210154351"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Mallika Rathore","raw_affiliation_strings":["Marvell Semiconductor, Boise, ID, USA"],"affiliations":[{"raw_affiliation_string":"Marvell Semiconductor, Boise, ID, USA","institution_ids":["https://openalex.org/I4210154351"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5012129149","display_name":"Weicheng Liu","orcid":"https://orcid.org/0000-0002-6561-026X"},"institutions":[{"id":"https://openalex.org/I59553526","display_name":"Stony Brook University","ror":"https://ror.org/05qghxh33","country_code":"US","type":"education","lineage":["https://openalex.org/I59553526"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Weicheng Liu","raw_affiliation_strings":["Stony Brook University, Stony Brook, NY, USA"],"affiliations":[{"raw_affiliation_string":"Stony Brook University, Stony Brook, NY, USA","institution_ids":["https://openalex.org/I59553526"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061262597","display_name":"Emre Salman","orcid":"https://orcid.org/0000-0001-6538-6803"},"institutions":[{"id":"https://openalex.org/I59553526","display_name":"Stony Brook University","ror":"https://ror.org/05qghxh33","country_code":"US","type":"education","lineage":["https://openalex.org/I59553526"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Emre Salman","raw_affiliation_strings":["Stony Brook University, Stony Brook, NY, USA"],"affiliations":[{"raw_affiliation_string":"Stony Brook University, Stony Brook, NY, USA","institution_ids":["https://openalex.org/I59553526"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5033656893","display_name":"Can Sitik","orcid":"https://orcid.org/0000-0003-0056-2137"},"institutions":[{"id":"https://openalex.org/I72816309","display_name":"Drexel University","ror":"https://ror.org/04bdffz58","country_code":"US","type":"education","lineage":["https://openalex.org/I72816309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Can Sitik","raw_affiliation_strings":["Drexel University, Philadelphia, PA, USA","Drexel University, Philadelphia, PA, USA;"],"affiliations":[{"raw_affiliation_string":"Drexel University, Philadelphia, PA, USA","institution_ids":["https://openalex.org/I72816309"]},{"raw_affiliation_string":"Drexel University, Philadelphia, PA, USA;","institution_ids":["https://openalex.org/I72816309"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5081080799","display_name":"Bar\u0131\u015f Ta\u015fk\u0131n","orcid":"https://orcid.org/0000-0002-7631-5696"},"institutions":[{"id":"https://openalex.org/I72816309","display_name":"Drexel University","ror":"https://ror.org/04bdffz58","country_code":"US","type":"education","lineage":["https://openalex.org/I72816309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Baris Taskin","raw_affiliation_strings":["Drexel University, Philadelphia, PA, USA","Drexel University, Philadelphia, PA, USA;"],"affiliations":[{"raw_affiliation_string":"Drexel University, Philadelphia, PA, USA","institution_ids":["https://openalex.org/I72816309"]},{"raw_affiliation_string":"Drexel University, Philadelphia, PA, USA;","institution_ids":["https://openalex.org/I72816309"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5040915860"],"corresponding_institution_ids":["https://openalex.org/I4210154351"],"apc_list":null,"apc_paid":null,"fwci":0.3946,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.66938407,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"301","last_page":"306"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/swing","display_name":"Swing","score":0.8671524524688721},{"id":"https://openalex.org/keywords/clock-network","display_name":"Clock network","score":0.6188292503356934},{"id":"https://openalex.org/keywords/flip-flop","display_name":"Flip-flop","score":0.609544575214386},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.5904568433761597},{"id":"https://openalex.org/keywords/robustness","display_name":"Robustness (evolution)","score":0.5863128304481506},{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.5758554339408875},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5073441863059998},{"id":"https://openalex.org/keywords/flops","display_name":"FLOPS","score":0.4687635600566864},{"id":"https://openalex.org/keywords/process-corners","display_name":"Process corners","score":0.4371461868286133},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.42844894528388977},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.3232209086418152},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.3010185956954956},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.2856394648551941},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2591514587402344},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2236384153366089},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.2161601483821869},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.10459348559379578},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.09596017003059387}],"concepts":[{"id":"https://openalex.org/C65655974","wikidata":"https://www.wikidata.org/wiki/Q14867674","display_name":"Swing","level":2,"score":0.8671524524688721},{"id":"https://openalex.org/C2778182565","wikidata":"https://www.wikidata.org/wiki/Q1752879","display_name":"Clock network","level":5,"score":0.6188292503356934},{"id":"https://openalex.org/C2781007278","wikidata":"https://www.wikidata.org/wiki/Q183406","display_name":"Flip-flop","level":3,"score":0.609544575214386},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.5904568433761597},{"id":"https://openalex.org/C63479239","wikidata":"https://www.wikidata.org/wiki/Q7353546","display_name":"Robustness (evolution)","level":3,"score":0.5863128304481506},{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.5758554339408875},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5073441863059998},{"id":"https://openalex.org/C3826847","wikidata":"https://www.wikidata.org/wiki/Q188768","display_name":"FLOPS","level":2,"score":0.4687635600566864},{"id":"https://openalex.org/C192615534","wikidata":"https://www.wikidata.org/wiki/Q7247268","display_name":"Process corners","level":3,"score":0.4371461868286133},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.42844894528388977},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.3232209086418152},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.3010185956954956},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.2856394648551941},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2591514587402344},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2236384153366089},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.2161601483821869},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.10459348559379578},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.09596017003059387},{"id":"https://openalex.org/C104317684","wikidata":"https://www.wikidata.org/wiki/Q7187","display_name":"Gene","level":2,"score":0.0},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2742060.2742095","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2742060.2742095","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 25th edition on Great Lakes Symposium on VLSI","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.9100000262260437,"id":"https://metadata.un.org/sdg/7"}],"awards":[{"id":"https://openalex.org/G8674216277","display_name":null,"funder_award_id":"2013-TJ-2449, 2013-TJ-2450","funder_id":"https://openalex.org/F4320306087","funder_display_name":"Semiconductor Research Corporation"}],"funders":[{"id":"https://openalex.org/F4320306087","display_name":"Semiconductor Research Corporation","ror":"https://ror.org/047z4n946"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W601886942","https://openalex.org/W1990371333","https://openalex.org/W1998525920","https://openalex.org/W2051230585","https://openalex.org/W2073989151","https://openalex.org/W2100332326","https://openalex.org/W2107305407","https://openalex.org/W2121169595","https://openalex.org/W2147323429","https://openalex.org/W2149009819","https://openalex.org/W2150322402","https://openalex.org/W2155062435","https://openalex.org/W2158881717","https://openalex.org/W2170265438","https://openalex.org/W2247480952","https://openalex.org/W2538516417","https://openalex.org/W6691163768"],"related_works":["https://openalex.org/W2282665643","https://openalex.org/W2087612346","https://openalex.org/W2164715378","https://openalex.org/W2144402314","https://openalex.org/W2075400577","https://openalex.org/W2144518356","https://openalex.org/W1933111433","https://openalex.org/W2121694082","https://openalex.org/W2128060653","https://openalex.org/W2112595964"],"abstract_inverted_index":{"Low":[0],"swing":[1,32,44,54,68,78,117],"clocking":[2],"is":[3,23,73,118,126],"a":[4,14,30,81,87],"well":[5],"known":[6],"technique":[7],"to":[8,36,115],"reduce":[9],"dynamic":[10],"power":[11,64,105],"consumption":[12,106],"of":[13,38,90,99,112,122],"clock":[15,33,59,88,116],"network.":[16],"A":[17],"novel":[18],"static":[19],"D":[20],"flip-flop":[21,72],"topology":[22,51,125],"proposed":[24,50,71,124],"that":[25],"can":[26],"reliably":[27],"operate":[28],"with":[29,75],"low":[31,53,67,77],"signal":[34],"(down":[35],"50%":[37],"the":[39,42,57,63,123],"VDD)":[40],"despite":[41],"full":[43],"data":[45],"and":[46,101,107,137],"output":[47],"signals.":[48],"The":[49,70,93,110,120],"enables":[52],"signals":[55],"within":[56],"entire":[58],"network,":[60],"thereby":[61],"maximizing":[62],"saved":[65],"by":[66,129],"operation.":[69],"compared":[74],"existing":[76],"flip-flops":[79],"using":[80],"45":[82],"nm":[83],"technology":[84],"node":[85],"at":[86,133],"frequency":[89],"1.5":[91],"GHz.":[92],"results":[94],"demonstrate":[95],"an":[96],"average":[97],"reduction":[98],"38.1%":[100],"44.4%":[102],"in,":[103],"respectively,":[104],"power-delay":[108],"product.":[109],"sensitivity":[111],"each":[113],"circuit":[114],"investigated.":[119],"robustness":[121],"also":[127],"demonstrated":[128],"ensuring":[130],"reliable":[131],"operation":[132],"various":[134],"process,":[135],"voltage,":[136],"temperature":[138],"corners.":[139]},"counts_by_year":[{"year":2019,"cited_by_count":2},{"year":2016,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
