{"id":"https://openalex.org/W2073863528","doi":"https://doi.org/10.1145/2742060.2742080","title":"Speed Binning Using Machine Learning And On-chip Slack Sensors","display_name":"Speed Binning Using Machine Learning And On-chip Slack Sensors","publication_year":2015,"publication_date":"2015-05-19","ids":{"openalex":"https://openalex.org/W2073863528","doi":"https://doi.org/10.1145/2742060.2742080","mag":"2073863528"},"language":"en","primary_location":{"id":"doi:10.1145/2742060.2742080","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2742060.2742080","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 25th edition on Great Lakes Symposium on VLSI","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5036369307","display_name":"Mehdi Sadi","orcid":"https://orcid.org/0000-0002-0468-7810"},"institutions":[{"id":"https://openalex.org/I140172145","display_name":"University of Connecticut","ror":"https://ror.org/02der9h97","country_code":"US","type":"education","lineage":["https://openalex.org/I140172145"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Mehdi Sadi","raw_affiliation_strings":["University of Connecticut, Storrs, CT, USA","University of Connecticut, Storrs, CT USA#TAB#"],"affiliations":[{"raw_affiliation_string":"University of Connecticut, Storrs, CT, USA","institution_ids":["https://openalex.org/I140172145"]},{"raw_affiliation_string":"University of Connecticut, Storrs, CT USA#TAB#","institution_ids":["https://openalex.org/I140172145"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102766705","display_name":"Mark Tehranipoor","orcid":"https://orcid.org/0009-0006-8410-2347"},"institutions":[{"id":"https://openalex.org/I140172145","display_name":"University of Connecticut","ror":"https://ror.org/02der9h97","country_code":"US","type":"education","lineage":["https://openalex.org/I140172145"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mark Tehranipoor","raw_affiliation_strings":["University of Connecticut, Storrs, CT, USA","University of Connecticut, Storrs, CT USA#TAB#"],"affiliations":[{"raw_affiliation_string":"University of Connecticut, Storrs, CT, USA","institution_ids":["https://openalex.org/I140172145"]},{"raw_affiliation_string":"University of Connecticut, Storrs, CT USA#TAB#","institution_ids":["https://openalex.org/I140172145"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101654149","display_name":"Xiaoxiao Wang","orcid":"https://orcid.org/0000-0001-7943-8360"},"institutions":[{"id":"https://openalex.org/I82880672","display_name":"Beihang University","ror":"https://ror.org/00wk2mp56","country_code":"CN","type":"education","lineage":["https://openalex.org/I82880672"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xiaoxiao Wang","raw_affiliation_strings":["Beihang University, Beijing, China","BeiHang University, BeiJing, China"],"affiliations":[{"raw_affiliation_string":"Beihang University, Beijing, China","institution_ids":["https://openalex.org/I82880672"]},{"raw_affiliation_string":"BeiHang University, BeiJing, China","institution_ids":["https://openalex.org/I82880672"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5084205383","display_name":"LeRoy Winemberg","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"LeRoy Winemberg","raw_affiliation_strings":["Freescale Semiconductor, Austin, TX, USA",", Freescale Semiconductor, Austin, TX, USA"],"affiliations":[{"raw_affiliation_string":"Freescale Semiconductor, Austin, TX, USA","institution_ids":[]},{"raw_affiliation_string":", Freescale Semiconductor, Austin, TX, USA","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5036369307"],"corresponding_institution_ids":["https://openalex.org/I140172145"],"apc_list":null,"apc_paid":null,"fwci":1.3146,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.80603329,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"155","last_page":"160"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9975000023841858,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.721208930015564},{"id":"https://openalex.org/keywords/sort","display_name":"sort","score":0.6634581685066223},{"id":"https://openalex.org/keywords/test-set","display_name":"Test set","score":0.5235230922698975},{"id":"https://openalex.org/keywords/critical-path-method","display_name":"Critical path method","score":0.522607147693634},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.48647233843803406},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.4749890863895416},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.44299179315567017},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.422324538230896},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.3591771125793457},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.3249121904373169},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.13755011558532715}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.721208930015564},{"id":"https://openalex.org/C88548561","wikidata":"https://www.wikidata.org/wiki/Q347599","display_name":"sort","level":2,"score":0.6634581685066223},{"id":"https://openalex.org/C169903167","wikidata":"https://www.wikidata.org/wiki/Q3985153","display_name":"Test set","level":2,"score":0.5235230922698975},{"id":"https://openalex.org/C115874739","wikidata":"https://www.wikidata.org/wiki/Q825377","display_name":"Critical path method","level":2,"score":0.522607147693634},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.48647233843803406},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.4749890863895416},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.44299179315567017},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.422324538230896},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.3591771125793457},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.3249121904373169},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.13755011558532715},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0},{"id":"https://openalex.org/C23123220","wikidata":"https://www.wikidata.org/wiki/Q816826","display_name":"Information retrieval","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2742060.2742080","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2742060.2742080","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 25th edition on Great Lakes Symposium on VLSI","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.4300000071525574}],"awards":[{"id":"https://openalex.org/G2818994099","display_name":null,"funder_award_id":"2422","funder_id":"https://openalex.org/F4320306087","funder_display_name":"Semiconductor Research Corporation"},{"id":"https://openalex.org/G5941973013","display_name":null,"funder_award_id":"CCF-1255898","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"}],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"},{"id":"https://openalex.org/F4320306087","display_name":"Semiconductor Research Corporation","ror":"https://ror.org/047z4n946"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":25,"referenced_works":["https://openalex.org/W1592930191","https://openalex.org/W1973688898","https://openalex.org/W1982515552","https://openalex.org/W2000174955","https://openalex.org/W2008396243","https://openalex.org/W2018013690","https://openalex.org/W2035787834","https://openalex.org/W2043367571","https://openalex.org/W2044647950","https://openalex.org/W2047663435","https://openalex.org/W2072546947","https://openalex.org/W2095665333","https://openalex.org/W2106315190","https://openalex.org/W2119616711","https://openalex.org/W2139315617","https://openalex.org/W2164754947","https://openalex.org/W2167253897","https://openalex.org/W2502164861","https://openalex.org/W4212990656","https://openalex.org/W4237835609","https://openalex.org/W4242547479","https://openalex.org/W6659337355","https://openalex.org/W6662585566","https://openalex.org/W6679327926","https://openalex.org/W6684323389"],"related_works":["https://openalex.org/W2091533492","https://openalex.org/W2082561435","https://openalex.org/W1588361197","https://openalex.org/W1991935474","https://openalex.org/W4319302805","https://openalex.org/W2341817401","https://openalex.org/W2162370517","https://openalex.org/W1953724919","https://openalex.org/W2914961374","https://openalex.org/W2128426877"],"abstract_inverted_index":{"Speed":[0],"binning":[1,23,51],"of":[2,8,13,31,65,89,112,118],"integrated":[3],"circuits":[4],"using":[5],"Fmax":[6,84],"test":[7,18,27,33],"a":[9,48,76,87,103],"SoC":[10,104],"requires":[11,36],"application":[12],"complex":[14],"functional":[15],"and":[16,35,82],"structural":[17],"patterns.":[19,42],"Today's":[20],"test-pattern-based":[21],"speed":[22,50],"techniques":[24,73],"incur":[25],"high":[26],"cost":[28],"in":[29,102],"terms":[30],"long":[32],"time":[34],"significant":[37],"effort":[38],"to":[39,74],"generate":[40],"effective":[41],"In":[43],"this":[44],"paper":[45],"we":[46],"propose":[47],"novel":[49],"flow":[52,98],"that":[53],"uses":[54],"path":[55],"timing":[56],"slacks,":[57],"extracted":[58,80],"with":[59],"robust":[60],"digital":[61],"embedded":[62],"sensor":[63],"IPs,":[64],"selected":[66],"critical/near-critical":[67],"paths.":[68],"We":[69],"apply":[70],"machine":[71],"learning":[72],"model":[75],"predictor":[77,114],"considering":[78],"the":[79,83,113,119],"slacks":[81],"values":[85],"from":[86],"set":[88],"randomly":[90],"tested":[91],"die":[92],"during":[93],"wafer":[94],"sort.":[95],"The":[96,109],"proposed":[97],"has":[99],"been":[100],"demonstrated":[101],"circuit":[105],"at":[106],"28/32nm":[107],"technology.":[108],"worst-case":[110],"miss-binning":[111],"is":[115],"within":[116],"6%":[117],"nominal":[120],"Fmax.":[121]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}