{"id":"https://openalex.org/W2089631698","doi":"https://doi.org/10.1145/2701126.2701213","title":"Implementation of high speed processor for computing convolution sum for DSP applications","display_name":"Implementation of high speed processor for computing convolution sum for DSP applications","publication_year":2015,"publication_date":"2015-01-08","ids":{"openalex":"https://openalex.org/W2089631698","doi":"https://doi.org/10.1145/2701126.2701213","mag":"2089631698"},"language":"en","primary_location":{"id":"doi:10.1145/2701126.2701213","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2701126.2701213","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 9th International Conference on Ubiquitous Information Management and Communication","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5044499339","display_name":"Prabir Saha","orcid":"https://orcid.org/0000-0001-6140-4680"},"institutions":[{"id":"https://openalex.org/I9523339","display_name":"National Institute of Technology Meghalaya","ror":"https://ror.org/020vd6n84","country_code":"IN","type":"education","lineage":["https://openalex.org/I9523339"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"P. Saha","raw_affiliation_strings":["NIT Meghalaya, Shillong, India","[NIT Meghalaya, Shillong, India]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"NIT Meghalaya, Shillong, India","institution_ids":["https://openalex.org/I9523339"]},{"raw_affiliation_string":"[NIT Meghalaya, Shillong, India]","institution_ids":["https://openalex.org/I9523339"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5007575867","display_name":"Deepak Kumar","orcid":"https://orcid.org/0000-0002-3399-2582"},"institutions":[{"id":"https://openalex.org/I9523339","display_name":"National Institute of Technology Meghalaya","ror":"https://ror.org/020vd6n84","country_code":"IN","type":"education","lineage":["https://openalex.org/I9523339"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"D. Kumar","raw_affiliation_strings":["NIT Meghalaya, Shillong, India","[NIT Meghalaya, Shillong, India]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"NIT Meghalaya, Shillong, India","institution_ids":["https://openalex.org/I9523339"]},{"raw_affiliation_string":"[NIT Meghalaya, Shillong, India]","institution_ids":["https://openalex.org/I9523339"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5020313758","display_name":"Abhijit Sharma","orcid":"https://orcid.org/0000-0002-1110-8936"},"institutions":[{"id":"https://openalex.org/I155837530","display_name":"National Institute of Technology Durgapur","ror":"https://ror.org/04ds0jm32","country_code":"IN","type":"education","lineage":["https://openalex.org/I155837530"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"A. Sharma","raw_affiliation_strings":["NIT Durgapur, Durgapur, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"NIT Durgapur, Durgapur, India","institution_ids":["https://openalex.org/I155837530"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/propagation-delay","display_name":"Propagation delay","score":0.7500451803207397},{"id":"https://openalex.org/keywords/convolution","display_name":"Convolution (computer science)","score":0.7166340351104736},{"id":"https://openalex.org/keywords/spice","display_name":"Spice","score":0.6819859743118286},{"id":"https://openalex.org/keywords/circular-convolution","display_name":"Circular convolution","score":0.6781548261642456},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6767878532409668},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6339256167411804},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.5263161659240723},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.48193955421447754},{"id":"https://openalex.org/keywords/overlap\u2013add-method","display_name":"Overlap\u2013add method","score":0.4427870810031891},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4367797076702118},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.41411030292510986},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.4102019667625427},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3769514560699463},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.36261868476867676},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.18705829977989197},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1450454294681549},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1260269582271576},{"id":"https://openalex.org/keywords/fourier-transform","display_name":"Fourier transform","score":0.10879543423652649},{"id":"https://openalex.org/keywords/artificial-neural-network","display_name":"Artificial neural network","score":0.08924862742424011}],"concepts":[{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.7500451803207397},{"id":"https://openalex.org/C45347329","wikidata":"https://www.wikidata.org/wiki/Q5166604","display_name":"Convolution (computer science)","level":3,"score":0.7166340351104736},{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.6819859743118286},{"id":"https://openalex.org/C194980680","wikidata":"https://www.wikidata.org/wiki/Q245450","display_name":"Circular convolution","level":5,"score":0.6781548261642456},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6767878532409668},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6339256167411804},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.5263161659240723},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.48193955421447754},{"id":"https://openalex.org/C181002996","wikidata":"https://www.wikidata.org/wiki/Q1611641","display_name":"Overlap\u2013add method","level":5,"score":0.4427870810031891},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4367797076702118},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.41411030292510986},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.4102019667625427},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3769514560699463},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.36261868476867676},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.18705829977989197},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1450454294681549},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1260269582271576},{"id":"https://openalex.org/C102519508","wikidata":"https://www.wikidata.org/wiki/Q6520159","display_name":"Fourier transform","level":2,"score":0.10879543423652649},{"id":"https://openalex.org/C50644808","wikidata":"https://www.wikidata.org/wiki/Q192776","display_name":"Artificial neural network","level":2,"score":0.08924862742424011},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0},{"id":"https://openalex.org/C203024314","wikidata":"https://www.wikidata.org/wiki/Q1365258","display_name":"Fourier analysis","level":3,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C76563020","wikidata":"https://www.wikidata.org/wiki/Q4817582","display_name":"Fractional Fourier transform","level":4,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2701126.2701213","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2701126.2701213","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 9th International Conference on Ubiquitous Information Management and Communication","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.8899999856948853}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1546246178","https://openalex.org/W1579530897","https://openalex.org/W1822327570","https://openalex.org/W1872648398","https://openalex.org/W1898944666","https://openalex.org/W2060815413","https://openalex.org/W2103060121","https://openalex.org/W2109874288","https://openalex.org/W2110827308","https://openalex.org/W2131647018","https://openalex.org/W2137958563","https://openalex.org/W2158572839","https://openalex.org/W2168857243","https://openalex.org/W2171882605","https://openalex.org/W2569807306","https://openalex.org/W2765691705"],"related_works":["https://openalex.org/W2778612236","https://openalex.org/W3106959200","https://openalex.org/W2556310577","https://openalex.org/W2133280289","https://openalex.org/W2267589039","https://openalex.org/W2382152453","https://openalex.org/W2778973728","https://openalex.org/W1796097737","https://openalex.org/W2126886659","https://openalex.org/W2089631698"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"we":[3],"report":[4],"on":[5],"transistor":[6],"level":[7],"(ASIC)":[8],"implementation":[9,77],"of":[10,25,36,78,84,115,132,137],"high":[11,47],"speed":[12,48],"processor":[13],"for":[14,18,42,74],"the":[15,34,37,75,116],"first":[16],"time,":[17],"computing":[19],"convolution":[20,29,79,120,140],"sum":[21,30],"(linear":[22],"and":[23,55,124],"circular)":[24],"two":[26],"sequences.":[27],"The":[28,51,62,93,112],"was":[31,57,121],"calculated":[32,105],"through":[33,59,106],"orientation":[35],"sequences":[38],"into":[39],"array":[40],"formation":[41],"parallel":[43],"processing,":[44],"owing":[45],"towards":[46],"architecture":[49],"design.":[50],"architectures":[52],"were":[53,104,141],"implemented":[54],"functionality":[56],"verified":[58],"spice":[60,107],"simulator.":[61],"mathematical":[63],"transformation":[64],"along":[65],"with":[66,89,128,145],"binary":[67],"coded":[68],"decimal(BCD)":[69],"arithmetic":[70],"have":[71],"been":[72],"incorporated":[73],"practical":[76],"sum,":[80],"ensure":[81],"substantial":[82],"reduction":[83],"propagation":[85,98,113,143],"delay":[86,114,144],"in":[87],"comparison":[88],"earlier":[90],"reported":[91],"architectures.":[92],"performance":[94,135],"parameters":[95,136],"such":[96],"as":[97],"delay,":[99],"dynamic":[100],"switching":[101,147],"power":[102,127,148],"consumption":[103],"using":[108],"90nm":[109],"CMOS":[110],"technology.":[111],"resulting":[117],"4-point":[118,138],"linear":[119],"only":[122],"~12.79ns":[123],"consumes":[125],"~27.56mW":[126],"a":[129],"layout":[130],"area":[131],"~9.06mm2.":[133],"Moreover,":[134],"circular":[139],"~14.8ns":[142],"~37.8mW":[146],"consumption.":[149]},"counts_by_year":[{"year":2018,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
