{"id":"https://openalex.org/W2027268759","doi":"https://doi.org/10.1145/2684746.2689103","title":"Cost-Effective Memory Architecture to Achieve Flexible Configuration and Efficient Data Transmission for Coarse-Grained Reconfigurable Array (Abstract Only)","display_name":"Cost-Effective Memory Architecture to Achieve Flexible Configuration and Efficient Data Transmission for Coarse-Grained Reconfigurable Array (Abstract Only)","publication_year":2015,"publication_date":"2015-02-10","ids":{"openalex":"https://openalex.org/W2027268759","doi":"https://doi.org/10.1145/2684746.2689103","mag":"2027268759"},"language":"en","primary_location":{"id":"doi:10.1145/2684746.2689103","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2684746.2689103","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100602455","display_name":"Yang Chen","orcid":"https://orcid.org/0009-0008-5752-1639"},"institutions":[{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]},{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Chen Yang","raw_affiliation_strings":["Institute of Microelectronics, Tsinghua University, Beijing, China"],"affiliations":[{"raw_affiliation_string":"Institute of Microelectronics, Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I99065089","https://openalex.org/I4210119392"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100358856","display_name":"Leibo Liu","orcid":"https://orcid.org/0000-0001-7548-4116"},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]},{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Leibo Liu","raw_affiliation_strings":["Institute of Microelectronics, Tsinghua University, Beijing, China"],"affiliations":[{"raw_affiliation_string":"Institute of Microelectronics, Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I99065089","https://openalex.org/I4210119392"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5054524841","display_name":"Shouyi Yin","orcid":"https://orcid.org/0000-0003-2309-572X"},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]},{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Shouyi Yin","raw_affiliation_strings":["Institute of Microelectronics, Tsinghua University, Beijing, China"],"affiliations":[{"raw_affiliation_string":"Institute of Microelectronics, Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I99065089","https://openalex.org/I4210119392"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5036023084","display_name":"Shaojun Wei","orcid":"https://orcid.org/0000-0001-5117-7920"},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]},{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Shaojun Wei","raw_affiliation_strings":["Institute of Microelectronics, Tsinghua University, Beijing, China"],"affiliations":[{"raw_affiliation_string":"Institute of Microelectronics, Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I99065089","https://openalex.org/I4210119392"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5100602455"],"corresponding_institution_ids":["https://openalex.org/I4210119392","https://openalex.org/I99065089"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.07119041,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"263","last_page":"263"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9976000189781189,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9976000189781189,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9861999750137329,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9797999858856201,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.853172779083252},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.5942355394363403},{"id":"https://openalex.org/keywords/bottleneck","display_name":"Bottleneck","score":0.5580334663391113},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5566205978393555},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5227237343788147},{"id":"https://openalex.org/keywords/memory-architecture","display_name":"Memory architecture","score":0.5135631561279297},{"id":"https://openalex.org/keywords/video-decoder","display_name":"Video decoder","score":0.5112175941467285},{"id":"https://openalex.org/keywords/memory-bandwidth","display_name":"Memory bandwidth","score":0.5092960596084595},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.47314727306365967},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4543449580669403},{"id":"https://openalex.org/keywords/data-access","display_name":"Data access","score":0.44289037585258484},{"id":"https://openalex.org/keywords/data-transmission","display_name":"Data transmission","score":0.44242992997169495},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.4185875952243805},{"id":"https://openalex.org/keywords/cache-only-memory-architecture","display_name":"Cache-only memory architecture","score":0.4139740467071533},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.3350435793399811},{"id":"https://openalex.org/keywords/decoding-methods","display_name":"Decoding methods","score":0.33242785930633545},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.2970125675201416},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.27330708503723145},{"id":"https://openalex.org/keywords/cache-coloring","display_name":"Cache coloring","score":0.23443475365638733},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.21201080083847046},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.13667082786560059},{"id":"https://openalex.org/keywords/database","display_name":"Database","score":0.07336065173149109}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.853172779083252},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.5942355394363403},{"id":"https://openalex.org/C2780513914","wikidata":"https://www.wikidata.org/wiki/Q18210350","display_name":"Bottleneck","level":2,"score":0.5580334663391113},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5566205978393555},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5227237343788147},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.5135631561279297},{"id":"https://openalex.org/C2776580754","wikidata":"https://www.wikidata.org/wiki/Q25098614","display_name":"Video decoder","level":3,"score":0.5112175941467285},{"id":"https://openalex.org/C188045654","wikidata":"https://www.wikidata.org/wiki/Q17148339","display_name":"Memory bandwidth","level":2,"score":0.5092960596084595},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.47314727306365967},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4543449580669403},{"id":"https://openalex.org/C47487241","wikidata":"https://www.wikidata.org/wiki/Q5227230","display_name":"Data access","level":2,"score":0.44289037585258484},{"id":"https://openalex.org/C557945733","wikidata":"https://www.wikidata.org/wiki/Q389772","display_name":"Data transmission","level":2,"score":0.44242992997169495},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.4185875952243805},{"id":"https://openalex.org/C3720319","wikidata":"https://www.wikidata.org/wiki/Q5015937","display_name":"Cache-only memory architecture","level":5,"score":0.4139740467071533},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.3350435793399811},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.33242785930633545},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.2970125675201416},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.27330708503723145},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.23443475365638733},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.21201080083847046},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.13667082786560059},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.07336065173149109},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2684746.2689103","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2684746.2689103","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.41999998688697815,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W2000039875","https://openalex.org/W2006027340","https://openalex.org/W2029447519","https://openalex.org/W2059260296","https://openalex.org/W2066814364","https://openalex.org/W2100027188","https://openalex.org/W2100149422","https://openalex.org/W2119162511","https://openalex.org/W2126919075","https://openalex.org/W2144426165","https://openalex.org/W2151014835","https://openalex.org/W2151103935"],"related_works":["https://openalex.org/W1974211070","https://openalex.org/W1942416056","https://openalex.org/W3180803030","https://openalex.org/W2096506606","https://openalex.org/W2011070474","https://openalex.org/W1959889508","https://openalex.org/W2047684617","https://openalex.org/W2145484885","https://openalex.org/W1978910209","https://openalex.org/W1975698617"],"abstract_inverted_index":{"The":[0,83,109,136,205],"memory":[1,76,103,112,138,206],"architecture":[2,218],"has":[3],"a":[4,13,45,215],"significant":[5],"effect":[6],"on":[7,185,214],"the":[8,60,80,101,152,179,182,192,195,221,225],"flexibility":[9],"and":[10,26,34,52,65,73,92,133,142,164,175],"performance":[11,146,171],"of":[12,29,50,154,159,173,181,194,227],"coarse-grained":[14],"reconfigurable":[15],"array":[16],"(CGRA),":[17],"which":[18,123],"can":[19,148,234],"be":[20,149,235],"restrained":[21],"due":[22],"to":[23,47,78,89,99,115,119,237],"configuration":[24,202],"overhead":[25],"large":[27],"latency":[28],"data":[30,35,75,111,117,127,132],"transmission.":[31],"Multi-context":[32],"structure":[33],"preloading":[36],"method":[37],"are":[38,140],"widely":[39],"used":[40,125],"in":[41,97,209,224],"popular":[42,229],"CGRAs":[43],"as":[44,126],"solution":[46],"bandwidth":[48],"bottlenecks":[49],"context":[51,71,85,94,197],"data.":[53,135],"However,":[54],"these":[55],"two":[56],"schemes":[57],"cannot":[58],"balance":[59],"computing":[61],"performance,":[62],"area":[63,156],"overhead,":[64],"flexibility.":[66],"This":[67],"paper":[68,211],"proposed":[69,137,208],"group-based":[70,84],"cache":[72,86],"multi-level":[74,110],"architectures":[77,139,207],"alleviate":[79],"bottleneck":[81],"problems.":[82],"was":[87,113],"designed":[88,114],"dynamically":[90],"transfer":[91],"buffer":[93],"inside":[95],"CGRA":[96,121,186,217],"order":[98],"relieve":[100],"off-chip":[102],"access":[104],"for":[105,129,203],"contexts":[106],"at":[107,151],"runtime.":[108],"add":[116],"memories":[118],"different":[120],"hierarchies,":[122],"were":[124,212],"buffers":[128],"reused":[130],"input":[131],"intermediate":[134],"efficient":[141],"cost-effective":[143],"so":[144],"that":[145],"improvement":[147],"achieved":[150,170],"cost":[153],"minor":[155],"overhead.":[157],"Experiments":[158],"H.264":[160],"video":[161],"decoding":[162],"program":[163],"scale":[165],"invariant":[166],"feature":[167],"transform":[168],"algorithm":[169],"improvements":[172],"19%":[174],"23%,":[176],"respectively.":[177],"Further,":[178],"complexity":[180],"applications":[183],"running":[184],"is":[187],"no":[188],"longer":[189],"restricted":[190],"by":[191],"capacity":[193],"on-chip":[196],"memory,":[198],"thereby":[199],"achieving":[200],"flexible":[201],"CGRA.":[204],"this":[210],"based":[213],"generic":[216],"derived":[219],"from":[220],"characteristics":[222],"found":[223],"majority":[226],"existing":[228],"CGRAs.":[230,239],"As":[231],"such,":[232],"they":[233],"applied":[236],"universal":[238]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}