{"id":"https://openalex.org/W2101252915","doi":"https://doi.org/10.1145/2684746.2689100","title":"Towards More Efficient Logic Blocks By Exploiting Biconditional Expansion (Abstract Only)","display_name":"Towards More Efficient Logic Blocks By Exploiting Biconditional Expansion (Abstract Only)","publication_year":2015,"publication_date":"2015-02-10","ids":{"openalex":"https://openalex.org/W2101252915","doi":"https://doi.org/10.1145/2684746.2689100","mag":"2101252915"},"language":"en","primary_location":{"id":"doi:10.1145/2684746.2689100","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2684746.2689100","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"http://infoscience.epfl.ch/record/204257","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5013403141","display_name":"Pierre-Emmanuel Gallardon","orcid":null},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":true,"raw_author_name":"Pierre-Emmanuel Gallardon","raw_affiliation_strings":["EPFL, Lausanne, Switzerland"],"affiliations":[{"raw_affiliation_string":"EPFL, Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5073822029","display_name":"Gain Kim","orcid":"https://orcid.org/0000-0002-3680-8816"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Gain Kim","raw_affiliation_strings":["EPFL, Lausanne, Switzerland"],"affiliations":[{"raw_affiliation_string":"EPFL, Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103004961","display_name":"Xifan Tang","orcid":"https://orcid.org/0000-0003-2203-3981"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Xifan Tang","raw_affiliation_strings":["EPFL, Lausanne, Switzerland"],"affiliations":[{"raw_affiliation_string":"EPFL, Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5023405941","display_name":"Luca Amar\u00f9","orcid":null},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Luca Amaru","raw_affiliation_strings":["EPFL, Lausanne, Switzerland"],"affiliations":[{"raw_affiliation_string":"EPFL, Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5072927296","display_name":"Giovanni De Micheli","orcid":"https://orcid.org/0000-0002-7827-3215"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Giovanni De Micheli","raw_affiliation_strings":["EPFL, Lausanne, Switzerland"],"affiliations":[{"raw_affiliation_string":"EPFL, Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5013403141"],"corresponding_institution_ids":["https://openalex.org/I5124864"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.07098387,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"262","last_page":"262"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.769781231880188},{"id":"https://openalex.org/keywords/logic-block","display_name":"Logic block","score":0.7214038968086243},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6794252991676331},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.6470005512237549},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.5429941415786743},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.5270215272903442},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.5099257230758667},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4892292022705078},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4868583083152771},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.455719918012619},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.4524598717689514},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.42061400413513184},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4169035255908966},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.34383147954940796},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3221747875213623},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.31201696395874023},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.28021687269210815},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.14051905274391174},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.07998183369636536}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.769781231880188},{"id":"https://openalex.org/C2778325283","wikidata":"https://www.wikidata.org/wiki/Q1125244","display_name":"Logic block","level":3,"score":0.7214038968086243},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6794252991676331},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.6470005512237549},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.5429941415786743},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.5270215272903442},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.5099257230758667},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4892292022705078},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4868583083152771},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.455719918012619},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.4524598717689514},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.42061400413513184},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4169035255908966},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.34383147954940796},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3221747875213623},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.31201696395874023},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.28021687269210815},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.14051905274391174},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.07998183369636536},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/2684746.2689100","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2684746.2689100","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"},{"id":"pmh:oai:infoscience.epfl.ch:204257","is_oa":true,"landing_page_url":"http://infoscience.epfl.ch/record/204257","pdf_url":null,"source":{"id":"https://openalex.org/S4306400487","display_name":"Infoscience (Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Text"}],"best_oa_location":{"id":"pmh:oai:infoscience.epfl.ch:204257","is_oa":true,"landing_page_url":"http://infoscience.epfl.ch/record/204257","pdf_url":null,"source":{"id":"https://openalex.org/S4306400487","display_name":"Infoscience (Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Text"},"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8700000047683716}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W3129977055","https://openalex.org/W2386022279","https://openalex.org/W1488117239","https://openalex.org/W1966764473","https://openalex.org/W4387905179","https://openalex.org/W2519443189","https://openalex.org/W4243936066","https://openalex.org/W4236027727","https://openalex.org/W4235101055","https://openalex.org/W1989216432"],"abstract_inverted_index":{"Nowadays,":[0],"Field":[1],"Programmable":[2],"Gate":[3],"Arrays":[4],"(FPGA)":[5],"exploit":[6],"Look-Up":[7],"Tables":[8],"(LUTs)":[9],"to":[10,26,109,116,186,193],"generate":[11],"logic":[12,83,101,119,130,220],"functions.":[13,120],"A":[14],"K-input":[15],"LUT":[16,90],"can":[17,204],"implement":[18,117,188],"any":[19],"Boolean":[20],"functions":[21,111],"with":[22,96,207],"K":[23],"inputs.":[24],"Thanks":[25],"this":[27],"flexibility,":[28],"LUTs":[29,52],"remained":[30],"conceptually":[31],"unchanged":[32],"in":[33,41,56,99,211,231],"FPGAs,":[34],"only":[35],"the":[36,44,100,148,172,181],"number":[37,61],"of":[38,62,167,175],"inputs":[39],"increased":[40],"time.":[42],"Unfortunately,":[43],"flexibility":[45],"does":[46],"not":[47],"come":[48],"for":[49],"free":[50],"and":[51,68,218,228,234],"have":[53],"non-negligible":[54],"costs":[55],"both":[57],"circuit-level":[58],"performances":[59],"(large":[60],"memories,":[63],"area":[64],"or":[65],"delay":[66,233],"penalties)":[67],"logic-level":[69],"capabilities":[70],"(limited":[71],"fan-out).":[72],"Here,":[73],"we":[74,86,104,141,222],"propose":[75],"an":[76,144],"FPGA":[77,145,157,197],"fabric":[78],"based":[79],"on":[80,224],"two":[81,122],"novel":[82,149],"blocks.":[84],"First,":[85],"introduce":[87],"a":[88,106,127,164,201,208],"new":[89],"design":[91],"showing":[92],"reduced":[93],"power":[94,173,235],"consumption":[95,174],"no":[97],"sacrifice":[98],"flexibility.":[102],"Then,":[103],"present":[105],"block":[107],"suited":[108],"arithmetic":[110,189,219],"but":[112],"preserving":[113],"enough":[114],"versatility":[115],"general":[118,217],"The":[121],"blocks":[123,150],"are":[124],"supported":[125],"by":[126,179],"recently":[128],"introduced":[129],"representation":[131],"called":[132],"Biconditional":[133],"Binary":[134],"Decision":[135],"Diagrams":[136],"(BBDDs).":[137],"Using":[138],"architectural-level":[139],"benchmarking,":[140],"showed":[142],"that":[143],"architecture":[146,183],"exploiting":[147],"performs":[151],"significantly":[152],"better":[153],"than":[154],"current":[155],"state-of-the-art":[156],"architectures":[158],"at":[159],"40nm":[160],"technological":[161],"node":[162],"over":[163],"large":[165,216],"set":[166],"test":[168],"circuits.":[169],"While":[170,214],"reducing":[171],"MCNC":[176],"big20":[177],"benchmarks":[178],"29%,":[180],"proposed":[182],"is":[184],"able":[185],"efficiently":[187],"circuits":[190],"as":[191],"compared":[192],"its":[194],"traditional":[195],"LUT-based":[196],"counterpart.":[198],"For":[199],"instance,":[200],"256-bit":[202],"adder":[203],"be":[205],"realized":[206],"43%":[209],"gain":[210],"area\u00d7delay":[212],"product.":[213],"considering":[215],"benchmarks,":[221],"observe,":[223],"average,":[225],"4%,":[226],"3%":[227],"10%":[229],"improvements":[230],"area,":[232],"respectively.":[236]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2016-06-24T00:00:00"}
