{"id":"https://openalex.org/W2068842950","doi":"https://doi.org/10.1145/2684746.2689089","title":"System-level Linking of Synthesised Hardware and Compiled Software Using a Higher-order Type System","display_name":"System-level Linking of Synthesised Hardware and Compiled Software Using a Higher-order Type System","publication_year":2015,"publication_date":"2015-02-10","ids":{"openalex":"https://openalex.org/W2068842950","doi":"https://doi.org/10.1145/2684746.2689089","mag":"2068842950"},"language":"en","primary_location":{"id":"doi:10.1145/2684746.2689089","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2684746.2689089","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5030827011","display_name":"Shane Fleming","orcid":"https://orcid.org/0000-0002-3224-278X"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Shane Fleming","raw_affiliation_strings":["Imperial College London, London, United Kingdom"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Imperial College London, London, United Kingdom","institution_ids":["https://openalex.org/I47508984"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081452934","display_name":"David B. Thomas","orcid":"https://orcid.org/0000-0002-9671-0917"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"David Thomas","raw_affiliation_strings":["Imperial College London, London, United Kingdom"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Imperial College London, London, United Kingdom","institution_ids":["https://openalex.org/I47508984"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5029829952","display_name":"George A. Constantinides","orcid":"https://orcid.org/0000-0002-0201-310X"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"George Constantinides","raw_affiliation_strings":["Imperial College London, London, United Kingdom"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Imperial College London, London, United Kingdom","institution_ids":["https://openalex.org/I47508984"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5072298249","display_name":"Dan R. Ghica","orcid":"https://orcid.org/0000-0002-4003-8893"},"institutions":[{"id":"https://openalex.org/I79619799","display_name":"University of Birmingham","ror":"https://ror.org/03angcq70","country_code":"GB","type":"education","lineage":["https://openalex.org/I79619799"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Dan Ghica","raw_affiliation_strings":["University of Birmingham, Birmingham, United Kingdom"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Birmingham, Birmingham, United Kingdom","institution_ids":["https://openalex.org/I79619799"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"214","last_page":"217"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9933000206947327,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9847000241279602,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7947356700897217},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.6626395583152771},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6384727954864502},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5375167727470398},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.5219998955726624},{"id":"https://openalex.org/keywords/component-based-software-engineering","display_name":"Component-based software engineering","score":0.48345956206321716},{"id":"https://openalex.org/keywords/software-system","display_name":"Software system","score":0.4511708915233612},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4473952054977417},{"id":"https://openalex.org/keywords/component","display_name":"Component (thermodynamics)","score":0.4100790023803711},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3845568299293518},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.3430076837539673}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7947356700897217},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.6626395583152771},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6384727954864502},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5375167727470398},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.5219998955726624},{"id":"https://openalex.org/C174683762","wikidata":"https://www.wikidata.org/wiki/Q609588","display_name":"Component-based software engineering","level":4,"score":0.48345956206321716},{"id":"https://openalex.org/C149091818","wikidata":"https://www.wikidata.org/wiki/Q2429814","display_name":"Software system","level":3,"score":0.4511708915233612},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4473952054977417},{"id":"https://openalex.org/C168167062","wikidata":"https://www.wikidata.org/wiki/Q1117970","display_name":"Component (thermodynamics)","level":2,"score":0.4100790023803711},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3845568299293518},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.3430076837539673},{"id":"https://openalex.org/C97355855","wikidata":"https://www.wikidata.org/wiki/Q11473","display_name":"Thermodynamics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1145/2684746.2689089","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2684746.2689089","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"},{"id":"pmh:oai:pure.atira.dk:openaire_cris_publications/6ea4a0f3-6bb9-42a7-8b33-8f790cc045bc","is_oa":false,"landing_page_url":"https://research.birmingham.ac.uk/en/publications/6ea4a0f3-6bb9-42a7-8b33-8f790cc045bc","pdf_url":null,"source":{"id":"https://openalex.org/S4306402634","display_name":"University of Birmingham Research Portal (University of Birmingham)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I79619799","host_organization_name":"University of Birmingham","host_organization_lineage":["https://openalex.org/I79619799"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Fleming, S, Thomas, D, Constantinides, G & Ghica, D 2015, System-level Linking of Synthesised Hardware and Compiled Software Using a Higher-order Type System. in Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA '15). Association for Computing Machinery , pp. 214-217, 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays , Monterey, California, United Kingdom, 22/02/15. https://doi.org/10.1145/2684746.2689089","raw_type":"contributionToPeriodical"},{"id":"pmh:oai:spiral.imperial.ac.uk:10044/1/53320","is_oa":false,"landing_page_url":"http://hdl.handle.net/10044/1/53320","pdf_url":null,"source":{"id":"https://openalex.org/S4306401396","display_name":"Spiral (Imperial College London)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I47508984","host_organization_name":"Imperial College London","host_organization_lineage":["https://openalex.org/I47508984"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"FPGA","raw_type":"Conference Paper"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G1796185948","display_name":null,"funder_award_id":"EP/K015214/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"},{"id":"https://openalex.org/G5299827457","display_name":null,"funder_award_id":"EP/K015168/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"},{"id":"https://openalex.org/G6181739867","display_name":"A higher-order approach to codesign - 27659","funder_award_id":"EP/K015214/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"}],"funders":[{"id":"https://openalex.org/F4320334627","display_name":"Engineering and Physical Sciences Research Council","ror":"https://ror.org/0439y7842"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W1493349649","https://openalex.org/W1970032753","https://openalex.org/W1990079240","https://openalex.org/W2022128349"],"related_works":["https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506","https://openalex.org/W4238190086","https://openalex.org/W2512656006","https://openalex.org/W4254068899","https://openalex.org/W2049353084","https://openalex.org/W2124353851","https://openalex.org/W2157036638","https://openalex.org/W2142425794"],"abstract_inverted_index":{"Devices":[0],"with":[1],"tightly":[2],"coupled":[3],"CPUs":[4],"and":[5,22,29,48,62,69,97,108],"FPGA":[6],"logic":[7],"allow":[8],"for":[9],"the":[10,40,51,86,118,134],"implementation":[11],"of":[12,85,123],"heterogeneous":[13],"applications":[14],"which":[15,64,126],"combine":[16],"multiple":[17],"components":[18,45,71],"written":[19],"in":[20,33,67,133],"hardware":[21,49,70,114,132],"software":[23,47,68,111,129],"languages,":[24],"including":[25],"first-party":[26],"source":[27],"code":[28],"third-party":[30],"IP.":[31],"Flexibility":[32],"component":[34],"relationships":[35],"is":[36,91],"important,":[37],"so":[38],"that":[39],"system":[41,61,90,119],"designer":[42],"can":[43],"move":[44],"between":[46],"as":[50,106],"application":[52],"design":[53,103],"evolves.":[54],"This":[55],"paper":[56],"presents":[57],"a":[58,121],"system-level":[59],"type":[60,89],"linker,":[63],"allows":[65],"functions":[66],"to":[72,93,101,110],"be":[73,94],"directly":[74],"linked":[75],"at":[76],"link":[77,127],"time,":[78],"without":[79],"requiring":[80],"any":[81],"modification":[82],"or":[83],"recompilation":[84],"components.":[87],"The":[88],"designed":[92],"language":[95],"agnostic,":[96],"exhibits":[98],"higher-order":[99],"features,":[100],"enables":[102],"patterns":[104],"such":[105],"notifications":[107],"callbacks":[109],"from":[112],"within":[113],"functions.":[115],"We":[116],"demonstrate":[117],"through":[120],"number":[122],"case":[124],"studies":[125],"compiled":[128],"against":[130],"synthesised":[131],"Xilinx":[135],"Zynq":[136],"platform.":[137]},"counts_by_year":[{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}