{"id":"https://openalex.org/W2016684773","doi":"https://doi.org/10.1145/2684746.2689082","title":"Technology Mapping into General Programmable Cells","display_name":"Technology Mapping into General Programmable Cells","publication_year":2015,"publication_date":"2015-02-10","ids":{"openalex":"https://openalex.org/W2016684773","doi":"https://doi.org/10.1145/2684746.2689082","mag":"2016684773"},"language":"en","primary_location":{"id":"doi:10.1145/2684746.2689082","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2684746.2689082","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5110450560","display_name":"Alan Mishchenko","orcid":"https://orcid.org/0009-0004-1303-6261"},"institutions":[{"id":"https://openalex.org/I95457486","display_name":"University of California, Berkeley","ror":"https://ror.org/01an7q238","country_code":"US","type":"education","lineage":["https://openalex.org/I95457486"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Alan Mishchenko","raw_affiliation_strings":["University of California Berkeley, Berkeley, CA, USA","University of California, Berkeley, Berkeley, CA USA"],"affiliations":[{"raw_affiliation_string":"University of California Berkeley, Berkeley, CA, USA","institution_ids":["https://openalex.org/I95457486"]},{"raw_affiliation_string":"University of California, Berkeley, Berkeley, CA USA","institution_ids":["https://openalex.org/I95457486"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5064568178","display_name":"Robert K. Brayton","orcid":"https://orcid.org/0000-0002-3861-1718"},"institutions":[{"id":"https://openalex.org/I95457486","display_name":"University of California, Berkeley","ror":"https://ror.org/01an7q238","country_code":"US","type":"education","lineage":["https://openalex.org/I95457486"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Robert Brayton","raw_affiliation_strings":["University of California Berkeley, Berkeley, CA, USA","University of California, Berkeley, Berkeley, CA USA"],"affiliations":[{"raw_affiliation_string":"University of California Berkeley, Berkeley, CA, USA","institution_ids":["https://openalex.org/I95457486"]},{"raw_affiliation_string":"University of California, Berkeley, Berkeley, CA USA","institution_ids":["https://openalex.org/I95457486"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100852727","display_name":"Wenyi Feng","orcid":null},"institutions":[{"id":"https://openalex.org/I4210110187","display_name":"Microsemi (United States)","ror":"https://ror.org/01mvkzj41","country_code":"US","type":"company","lineage":["https://openalex.org/I4210110187"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Wenyi Feng","raw_affiliation_strings":["Microsemi Corporation, San Jose, CA, USA"],"affiliations":[{"raw_affiliation_string":"Microsemi Corporation, San Jose, CA, USA","institution_ids":["https://openalex.org/I4210110187"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5076157491","display_name":"Jonathan Greene","orcid":"https://orcid.org/0000-0002-7038-6629"},"institutions":[{"id":"https://openalex.org/I4210110187","display_name":"Microsemi (United States)","ror":"https://ror.org/01mvkzj41","country_code":"US","type":"company","lineage":["https://openalex.org/I4210110187"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jonathan Greene","raw_affiliation_strings":["Microsemi Corporation, San Jose, CA, USA"],"affiliations":[{"raw_affiliation_string":"Microsemi Corporation, San Jose, CA, USA","institution_ids":["https://openalex.org/I4210110187"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5110450560"],"corresponding_institution_ids":["https://openalex.org/I95457486"],"apc_list":null,"apc_paid":null,"fwci":1.9875,"has_fulltext":false,"cited_by_count":15,"citation_normalized_percentile":{"value":0.86140259,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"70","last_page":"73"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8170490264892578},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7547058463096619},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.7516226768493652},{"id":"https://openalex.org/keywords/programmable-logic-array","display_name":"Programmable logic array","score":0.6443881392478943},{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.61933434009552},{"id":"https://openalex.org/keywords/macrocell-array","display_name":"Macrocell array","score":0.5725089907646179},{"id":"https://openalex.org/keywords/function","display_name":"Function (biology)","score":0.5369614958763123},{"id":"https://openalex.org/keywords/simple-programmable-logic-device","display_name":"Simple programmable logic device","score":0.5135898590087891},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4960092008113861},{"id":"https://openalex.org/keywords/boolean-function","display_name":"Boolean function","score":0.48717349767684937},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.47044768929481506},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.41398075222969055},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.39660072326660156},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.35615095496177673},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.32965004444122314},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.26961302757263184}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8170490264892578},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7547058463096619},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.7516226768493652},{"id":"https://openalex.org/C182322920","wikidata":"https://www.wikidata.org/wiki/Q2112217","display_name":"Programmable logic array","level":3,"score":0.6443881392478943},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.61933434009552},{"id":"https://openalex.org/C142278197","wikidata":"https://www.wikidata.org/wiki/Q4284934","display_name":"Macrocell array","level":5,"score":0.5725089907646179},{"id":"https://openalex.org/C14036430","wikidata":"https://www.wikidata.org/wiki/Q3736076","display_name":"Function (biology)","level":2,"score":0.5369614958763123},{"id":"https://openalex.org/C34370810","wikidata":"https://www.wikidata.org/wiki/Q3961319","display_name":"Simple programmable logic device","level":5,"score":0.5135898590087891},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4960092008113861},{"id":"https://openalex.org/C187455244","wikidata":"https://www.wikidata.org/wiki/Q942353","display_name":"Boolean function","level":2,"score":0.48717349767684937},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.47044768929481506},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.41398075222969055},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.39660072326660156},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.35615095496177673},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.32965004444122314},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.26961302757263184},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C78458016","wikidata":"https://www.wikidata.org/wiki/Q840400","display_name":"Evolutionary biology","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2684746.2689082","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2684746.2689082","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.4399999976158142,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W1503377936","https://openalex.org/W1972355764","https://openalex.org/W1974514467","https://openalex.org/W1996198117","https://openalex.org/W2025617772","https://openalex.org/W2050779425","https://openalex.org/W2070101640","https://openalex.org/W2078644645","https://openalex.org/W2082947990","https://openalex.org/W2099134576","https://openalex.org/W2100955320","https://openalex.org/W2115967254","https://openalex.org/W2120569261","https://openalex.org/W2131713326","https://openalex.org/W2131972012","https://openalex.org/W2159034123","https://openalex.org/W2159111323","https://openalex.org/W2233304325","https://openalex.org/W6667977738","https://openalex.org/W6669805704","https://openalex.org/W6683558733"],"related_works":["https://openalex.org/W1528933814","https://openalex.org/W3117015220","https://openalex.org/W3013792460","https://openalex.org/W2466591189","https://openalex.org/W1904803855","https://openalex.org/W3022525969","https://openalex.org/W2014165129","https://openalex.org/W4389045693","https://openalex.org/W2376859467","https://openalex.org/W2125609625"],"abstract_inverted_index":{"Field-Programmable":[0],"Gate":[1],"Arrays":[2],"(FPGA)":[3],"implement":[4,18],"logic":[5,118],"functions":[6],"using":[7],"programmable":[8,126],"cells,":[9],"such":[10],"as":[11],"K-input":[12,93],"lookup-tables":[13],"(K-LUTs).":[14],"A":[15],"K-LUT":[16],"can":[17,107],"any":[19],"Boolean":[20],"function":[21],"with":[22,59,103],"K":[23,43],"inputs":[24,106],"and":[25,36,55,71,98,115,120,128,149],"one":[26],"output.":[27],"Methods":[28],"for":[29,48,64],"mapping":[30,65,146],"into":[31,66,91],"K-LUTs":[32],"are":[33,69],"extensively":[34],"researched":[35],"widely":[37],"used.":[38],"Recently,":[39],"cells":[40,68,94],"other":[41,99],"than":[42],"LUTs":[44,54,58],"have":[45],"been":[46],"explored,":[47],"example,":[49],"those":[50,56],"composed":[51,133],"of":[52,124,134,136,154],"several":[53,60],"combining":[57],"gates.":[61,101],"Known":[62],"methods":[63],"these":[67],"specialized":[70],"complicated,":[72],"requiring":[73],"a":[74,85,117,121,125],"substantial":[75],"effort":[76],"to":[77,88,104,151],"evaluate":[78],"custom":[79],"cell":[80],"architectures.":[81],"This":[82],"paper":[83],"presents":[84],"general":[86],"approach":[87],"efficiently":[89],"map":[90],"single-output":[92],"containing":[95],"LUTs,":[96],"MUXes,":[97],"elementary":[100],"Cells":[102],"16":[105],"be":[108],"handled.":[109],"The":[110],"mapper":[111],"is":[112,147],"fully":[113],"automated":[114],"takes":[116],"network":[119,132],"symbolic":[122],"description":[123],"cell,":[127],"produces":[129],"an":[130],"optimized":[131],"instances":[135],"the":[137],"given":[138],"cell.":[139],"Past":[140],"work":[141],"on":[142],"delay/area":[143],"optimization":[144],"during":[145],"applicable":[148],"leads":[150],"good":[152],"quality":[153],"results.":[155]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":1},{"year":2023,"cited_by_count":2},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":3},{"year":2018,"cited_by_count":3},{"year":2016,"cited_by_count":3}],"updated_date":"2026-03-13T16:22:10.518609","created_date":"2025-10-10T00:00:00"}