{"id":"https://openalex.org/W1974751828","doi":"https://doi.org/10.1145/2684746.2689074","title":"Take the Highway","display_name":"Take the Highway","publication_year":2015,"publication_date":"2015-02-10","ids":{"openalex":"https://openalex.org/W1974751828","doi":"https://doi.org/10.1145/2684746.2689074","mag":"1974751828"},"language":"en","primary_location":{"id":"doi:10.1145/2684746.2689074","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2684746.2689074","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5010814272","display_name":"Mohamed S. Abdelfattah","orcid":"https://orcid.org/0000-0002-4568-8932"},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Mohamed S. Abdelfattah","raw_affiliation_strings":["University of Toronto, Toronto, ON, Canada","University of Toronto, Toronto, On, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Toronto, Toronto, ON, Canada","institution_ids":["https://openalex.org/I185261750"]},{"raw_affiliation_string":"University of Toronto, Toronto, On, Canada","institution_ids":["https://openalex.org/I185261750"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5071905570","display_name":"Andrew Bitar","orcid":null},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Andrew Bitar","raw_affiliation_strings":["University of Toronto, Toronto, ON, Canada","University of Toronto, Toronto, On, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Toronto, Toronto, ON, Canada","institution_ids":["https://openalex.org/I185261750"]},{"raw_affiliation_string":"University of Toronto, Toronto, On, Canada","institution_ids":["https://openalex.org/I185261750"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5030184404","display_name":"Vaughn Betz","orcid":"https://orcid.org/0000-0003-0528-6493"},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Vaughn Betz","raw_affiliation_strings":["University of Toronto, Toronto, ON, Canada","University of Toronto, Toronto, On, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Toronto, Toronto, ON, Canada","institution_ids":["https://openalex.org/I185261750"]},{"raw_affiliation_string":"University of Toronto, Toronto, On, Canada","institution_ids":["https://openalex.org/I185261750"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":6.3118,"has_fulltext":false,"cited_by_count":36,"citation_normalized_percentile":{"value":0.96668672,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"98","last_page":"107"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9966999888420105,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8048625588417053},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6987909078598022},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6387388706207275},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.6371791362762451},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.6355012655258179},{"id":"https://openalex.org/keywords/ethernet","display_name":"Ethernet","score":0.5908006429672241},{"id":"https://openalex.org/keywords/leverage","display_name":"Leverage (statistics)","score":0.5409475564956665},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.507806122303009},{"id":"https://openalex.org/keywords/network-interface","display_name":"Network interface","score":0.4367201030254364},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4142093360424042},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3494512438774109},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.2164178192615509},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09751284122467041}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8048625588417053},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6987909078598022},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6387388706207275},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.6371791362762451},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.6355012655258179},{"id":"https://openalex.org/C172173386","wikidata":"https://www.wikidata.org/wiki/Q79984","display_name":"Ethernet","level":2,"score":0.5908006429672241},{"id":"https://openalex.org/C153083717","wikidata":"https://www.wikidata.org/wiki/Q6535263","display_name":"Leverage (statistics)","level":2,"score":0.5409475564956665},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.507806122303009},{"id":"https://openalex.org/C103987645","wikidata":"https://www.wikidata.org/wiki/Q985806","display_name":"Network interface","level":3,"score":0.4367201030254364},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4142093360424042},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3494512438774109},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.2164178192615509},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09751284122467041},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2684746.2689074","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2684746.2689074","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":24,"referenced_works":["https://openalex.org/W1501077214","https://openalex.org/W1988766139","https://openalex.org/W1999823427","https://openalex.org/W2013272814","https://openalex.org/W2023146792","https://openalex.org/W2026844540","https://openalex.org/W2046105216","https://openalex.org/W2076069927","https://openalex.org/W2082295213","https://openalex.org/W2097876246","https://openalex.org/W2100263028","https://openalex.org/W2112678088","https://openalex.org/W2118231264","https://openalex.org/W2120538858","https://openalex.org/W2131166199","https://openalex.org/W2133156997","https://openalex.org/W2140956115","https://openalex.org/W2142628816","https://openalex.org/W2157629805","https://openalex.org/W2158565219","https://openalex.org/W2170293694","https://openalex.org/W2171825402","https://openalex.org/W2922814486","https://openalex.org/W4255469022"],"related_works":["https://openalex.org/W3010619501","https://openalex.org/W2161995522","https://openalex.org/W2889326901","https://openalex.org/W2043881088","https://openalex.org/W2390899382","https://openalex.org/W2545310974","https://openalex.org/W1970476643","https://openalex.org/W2160431944","https://openalex.org/W4283687353","https://openalex.org/W2379944253"],"abstract_inverted_index":{"We":[0,47],"explore":[1],"the":[2,12,27,31,45,57,66,103],"addition":[3],"of":[4,36,63,87],"a":[5,108],"fast":[6],"embedded":[7,32,67,79,104],"network-on-chip":[8],"(NoC)":[9],"to":[10,41,116],"augment":[11],"FPGA's":[13],"existing":[14],"wires":[15,90],"and":[16,18,30,39,51,55,93,97],"switches,":[17],"help":[19],"interconnect":[20],"large":[21],"applications.":[22],"A":[23],"flexible":[24],"interface":[25],"between":[26],"FPGA":[28],"fabric":[29],"NoC":[33,80,105],"allows":[34],"modules":[35],"varying":[37],"widths":[38],"frequencies":[40],"transport":[42],"data":[43],"over":[44],"NoC.":[46,68],"study":[48,72],"both":[49],"latency-insensitive":[50],"latency-sensitive":[52],"design":[53,95],"styles":[54],"present":[56],"constraints":[58],"for":[59],"implementing":[60],"each":[61],"type":[62],"communication":[64],"on":[65,119],"Our":[69],"application":[70],"case":[71],"with":[73],"image":[74],"compression":[75],"shows":[76],"that":[77,112],"an":[78],"improves":[81],"frequency":[82],"by":[83,91],"10-80%,":[84],"reduces":[85],"utilization":[86],"scarce":[88],"long":[89],"40%":[92],"makes":[94],"easier":[96],"more":[98],"predictable.":[99],"Additionally,":[100],"we":[101],"leverage":[102],"in":[106],"creating":[107],"programmable":[109],"Ethernet":[110],"switch":[111],"can":[113],"support":[114],"up":[115],"819":[117],"Gb/s":[118],"FPGAs.":[120]},"counts_by_year":[{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":4},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":4},{"year":2018,"cited_by_count":5},{"year":2017,"cited_by_count":4},{"year":2016,"cited_by_count":4},{"year":2015,"cited_by_count":5}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2016-06-24T00:00:00"}