{"id":"https://openalex.org/W2061230651","doi":"https://doi.org/10.1145/2684746.2689063","title":"Mapping-Aware Constrained Scheduling for LUT-Based FPGAs","display_name":"Mapping-Aware Constrained Scheduling for LUT-Based FPGAs","publication_year":2015,"publication_date":"2015-02-10","ids":{"openalex":"https://openalex.org/W2061230651","doi":"https://doi.org/10.1145/2684746.2689063","mag":"2061230651"},"language":"en","primary_location":{"id":"doi:10.1145/2684746.2689063","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2684746.2689063","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5110774377","display_name":"Mingxing Tan","orcid":null},"institutions":[{"id":"https://openalex.org/I205783295","display_name":"Cornell University","ror":"https://ror.org/05bnh6r87","country_code":"US","type":"education","lineage":["https://openalex.org/I205783295"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Mingxing Tan","raw_affiliation_strings":["Cornell University, Ithaca, NY, USA"],"affiliations":[{"raw_affiliation_string":"Cornell University, Ithaca, NY, USA","institution_ids":["https://openalex.org/I205783295"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5030894829","display_name":"Steve Dai","orcid":"https://orcid.org/0000-0002-5045-1964"},"institutions":[{"id":"https://openalex.org/I205783295","display_name":"Cornell University","ror":"https://ror.org/05bnh6r87","country_code":"US","type":"education","lineage":["https://openalex.org/I205783295"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Steve Dai","raw_affiliation_strings":["Cornell University, Ithaca, NY, USA"],"affiliations":[{"raw_affiliation_string":"Cornell University, Ithaca, NY, USA","institution_ids":["https://openalex.org/I205783295"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5035704218","display_name":"Udit Gupta","orcid":"https://orcid.org/0000-0002-9118-0961"},"institutions":[{"id":"https://openalex.org/I205783295","display_name":"Cornell University","ror":"https://ror.org/05bnh6r87","country_code":"US","type":"education","lineage":["https://openalex.org/I205783295"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Udit Gupta","raw_affiliation_strings":["Cornell University, Ithaca, NY, USA"],"affiliations":[{"raw_affiliation_string":"Cornell University, Ithaca, NY, USA","institution_ids":["https://openalex.org/I205783295"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5037210004","display_name":"Zhiru Zhang","orcid":"https://orcid.org/0000-0002-0778-0308"},"institutions":[{"id":"https://openalex.org/I205783295","display_name":"Cornell University","ror":"https://ror.org/05bnh6r87","country_code":"US","type":"education","lineage":["https://openalex.org/I205783295"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Zhiru Zhang","raw_affiliation_strings":["Cornell University, Ithaca, NY, USA"],"affiliations":[{"raw_affiliation_string":"Cornell University, Ithaca, NY, USA","institution_ids":["https://openalex.org/I205783295"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5110774377"],"corresponding_institution_ids":["https://openalex.org/I205783295"],"apc_list":null,"apc_paid":null,"fwci":2.3088,"has_fulltext":false,"cited_by_count":21,"citation_normalized_percentile":{"value":0.88073236,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"190","last_page":"199"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8032535314559937},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.767590343952179},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7520629167556763},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.5975601673126221},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5337316393852234},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.4819902777671814},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4339732825756073},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.4302385449409485},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.42603054642677307},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3828809857368469},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.37400197982788086},{"id":"https://openalex.org/keywords/real-time-computing","display_name":"Real-time computing","score":0.3203848600387573},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.16120892763137817},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.08451303839683533}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8032535314559937},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.767590343952179},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7520629167556763},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.5975601673126221},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5337316393852234},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.4819902777671814},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4339732825756073},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.4302385449409485},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.42603054642677307},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3828809857368469},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.37400197982788086},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.3203848600387573},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.16120892763137817},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.08451303839683533},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1145/2684746.2689063","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2684746.2689063","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.710.234","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.710.234","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://csl.cornell.edu/%7Emingxing/papers/FPGA15_tan.pdf","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.719.2516","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.719.2516","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.csl.cornell.edu/%7Ezhiruz/pdfs/maps-fpga2015.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"},{"id":"https://openalex.org/F4320314786","display_name":"Xilinx","ror":"https://ror.org/01rb7bk56"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":35,"referenced_works":["https://openalex.org/W205961229","https://openalex.org/W1686420892","https://openalex.org/W1905608265","https://openalex.org/W1984866458","https://openalex.org/W1985457698","https://openalex.org/W1996464317","https://openalex.org/W2008086810","https://openalex.org/W2013784404","https://openalex.org/W2025617772","https://openalex.org/W2030287398","https://openalex.org/W2041460909","https://openalex.org/W2047631674","https://openalex.org/W2057108708","https://openalex.org/W2071189607","https://openalex.org/W2073137766","https://openalex.org/W2085884196","https://openalex.org/W2093842169","https://openalex.org/W2095595785","https://openalex.org/W2104451751","https://openalex.org/W2105715355","https://openalex.org/W2110085199","https://openalex.org/W2122078405","https://openalex.org/W2138265054","https://openalex.org/W2147088458","https://openalex.org/W2149239312","https://openalex.org/W2153185479","https://openalex.org/W2153801278","https://openalex.org/W2156499539","https://openalex.org/W2166029537","https://openalex.org/W2171775842","https://openalex.org/W2916086000","https://openalex.org/W3145042860","https://openalex.org/W4239489018","https://openalex.org/W4241148135","https://openalex.org/W4246166885"],"related_works":["https://openalex.org/W2155289750","https://openalex.org/W2159724425","https://openalex.org/W4231267350","https://openalex.org/W2120935739","https://openalex.org/W2117956479","https://openalex.org/W2053477566","https://openalex.org/W2101075828","https://openalex.org/W4255564979","https://openalex.org/W2123535323","https://openalex.org/W2142474790"],"abstract_inverted_index":{"Scheduling":[0],"plays":[1],"a":[2,53,69,78],"central":[3],"role":[4],"in":[5],"high-level":[6],"synthesis,":[7],"as":[8],"it":[9,44],"inserts":[10],"clock":[11],"boundaries":[12],"into":[13],"the":[14,21,27],"untimed":[15],"behavioral":[16],"model":[17],"and":[18,24],"greatly":[19],"impacts":[20],"performance,":[22],"power,":[23],"area":[25],"of":[26,37,41,55,81],"synthesized":[28],"circuits.":[29],"While":[30],"current":[31],"scheduling":[32],"techniques":[33],"can":[34,73],"make":[35],"use":[36],"pre-characterized":[38],"delay":[39],"values":[40],"individual":[42],"operations,":[43],"is":[45,63],"difficult":[46],"to":[47,76],"obtain":[48],"accurate":[49],"timing":[50],"estimation":[51],"on":[52],"cluster":[54],"operations":[56],"without":[57],"considering":[58],"technology":[59],"mapping.":[60],"This":[61],"limitation":[62],"particularly":[64],"pronounced":[65],"for":[66],"FPGAs":[67],"where":[68],"large":[70],"logic":[71],"network":[72],"be":[74],"mapped":[75],"only":[77],"few":[79],"levels":[80],"look-up":[82],"tables":[83],"(LUT).":[84]},"counts_by_year":[{"year":2024,"cited_by_count":4},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":3}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}