{"id":"https://openalex.org/W2085828379","doi":"https://doi.org/10.1145/2674095.2674096","title":"Performance Evaluation of Dynamic Circuit Specialization on Xilinx FPGAs","display_name":"Performance Evaluation of Dynamic Circuit Specialization on Xilinx FPGAs","publication_year":2014,"publication_date":"2014-09-09","ids":{"openalex":"https://openalex.org/W2085828379","doi":"https://doi.org/10.1145/2674095.2674096","mag":"2085828379"},"language":"en","primary_location":{"id":"doi:10.1145/2674095.2674096","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2674095.2674096","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the FPGA World Conference 2014","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5086835710","display_name":"Amit Kulkarni","orcid":"https://orcid.org/0000-0001-7548-3332"},"institutions":[{"id":"https://openalex.org/I32597200","display_name":"Ghent University","ror":"https://ror.org/00cv9y106","country_code":"BE","type":"education","lineage":["https://openalex.org/I32597200"]}],"countries":["BE"],"is_corresponding":true,"raw_author_name":"Amit Kulkarni","raw_affiliation_strings":["ELIS department, Computer Systems Lab, Ghent University, Sint-Pietersnieuwstraat 41, Ghent B-9000, Belgium"],"affiliations":[{"raw_affiliation_string":"ELIS department, Computer Systems Lab, Ghent University, Sint-Pietersnieuwstraat 41, Ghent B-9000, Belgium","institution_ids":["https://openalex.org/I32597200"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5020622964","display_name":"Karel Heyse","orcid":null},"institutions":[{"id":"https://openalex.org/I32597200","display_name":"Ghent University","ror":"https://ror.org/00cv9y106","country_code":"BE","type":"education","lineage":["https://openalex.org/I32597200"]}],"countries":["BE"],"is_corresponding":false,"raw_author_name":"Karel Heyse","raw_affiliation_strings":["ELIS department, Computer Systems Lab, Ghent University, Sint-Pietersnieuwstraat 41, Ghent B-9000, Belgium"],"affiliations":[{"raw_affiliation_string":"ELIS department, Computer Systems Lab, Ghent University, Sint-Pietersnieuwstraat 41, Ghent B-9000, Belgium","institution_ids":["https://openalex.org/I32597200"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5074378105","display_name":"Tom Davidson","orcid":"https://orcid.org/0000-0001-8059-6235"},"institutions":[{"id":"https://openalex.org/I32597200","display_name":"Ghent University","ror":"https://ror.org/00cv9y106","country_code":"BE","type":"education","lineage":["https://openalex.org/I32597200"]}],"countries":["BE"],"is_corresponding":false,"raw_author_name":"Tom Davidson","raw_affiliation_strings":["ELIS department, Computer Systems Lab, Ghent University, Sint-Pietersnieuwstraat 41, Ghent B-9000, Belgium"],"affiliations":[{"raw_affiliation_string":"ELIS department, Computer Systems Lab, Ghent University, Sint-Pietersnieuwstraat 41, Ghent B-9000, Belgium","institution_ids":["https://openalex.org/I32597200"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5004502321","display_name":"Dirk Stroobandt","orcid":"https://orcid.org/0000-0002-4477-5313"},"institutions":[{"id":"https://openalex.org/I32597200","display_name":"Ghent University","ror":"https://ror.org/00cv9y106","country_code":"BE","type":"education","lineage":["https://openalex.org/I32597200"]}],"countries":["BE"],"is_corresponding":false,"raw_author_name":"Dirk Stroobandt","raw_affiliation_strings":["ELIS department, Computer Systems Lab, Ghent University, Sint-Pietersnieuwstraat 41, Ghent B-9000, Belgium"],"affiliations":[{"raw_affiliation_string":"ELIS department, Computer Systems Lab, Ghent University, Sint-Pietersnieuwstraat 41, Ghent B-9000, Belgium","institution_ids":["https://openalex.org/I32597200"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5086835710"],"corresponding_institution_ids":["https://openalex.org/I32597200"],"apc_list":null,"apc_paid":null,"fwci":3.1435,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.91735537,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.9365156888961792},{"id":"https://openalex.org/keywords/virtex","display_name":"Virtex","score":0.7866954803466797},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7352091073989868},{"id":"https://openalex.org/keywords/parameterized-complexity","display_name":"Parameterized complexity","score":0.692473828792572},{"id":"https://openalex.org/keywords/finite-impulse-response","display_name":"Finite impulse response","score":0.6238216161727905},{"id":"https://openalex.org/keywords/bitstream","display_name":"Bitstream","score":0.5773122310638428},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5523149967193604},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.4674542546272278},{"id":"https://openalex.org/keywords/filter","display_name":"Filter (signal processing)","score":0.45008203387260437},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3862035572528839},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.11277011036872864},{"id":"https://openalex.org/keywords/decoding-methods","display_name":"Decoding methods","score":0.05849480628967285}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.9365156888961792},{"id":"https://openalex.org/C2777674469","wikidata":"https://www.wikidata.org/wiki/Q20741011","display_name":"Virtex","level":3,"score":0.7866954803466797},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7352091073989868},{"id":"https://openalex.org/C165464430","wikidata":"https://www.wikidata.org/wiki/Q1570441","display_name":"Parameterized complexity","level":2,"score":0.692473828792572},{"id":"https://openalex.org/C198386975","wikidata":"https://www.wikidata.org/wiki/Q117785","display_name":"Finite impulse response","level":2,"score":0.6238216161727905},{"id":"https://openalex.org/C136695289","wikidata":"https://www.wikidata.org/wiki/Q415568","display_name":"Bitstream","level":3,"score":0.5773122310638428},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5523149967193604},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.4674542546272278},{"id":"https://openalex.org/C106131492","wikidata":"https://www.wikidata.org/wiki/Q3072260","display_name":"Filter (signal processing)","level":2,"score":0.45008203387260437},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3862035572528839},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.11277011036872864},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.05849480628967285},{"id":"https://openalex.org/C31972630","wikidata":"https://www.wikidata.org/wiki/Q844240","display_name":"Computer vision","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/2674095.2674096","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2674095.2674096","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the FPGA World Conference 2014","raw_type":"proceedings-article"},{"id":"pmh:oai:archive.ugent.be:5757460","is_oa":false,"landing_page_url":"http://hdl.handle.net/1854/LU-5757460","pdf_url":null,"source":{"id":"https://openalex.org/S4306400478","display_name":"Ghent University Academic Bibliography (Ghent University)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I32597200","host_organization_name":"Ghent University","host_organization_lineage":["https://openalex.org/I32597200"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"ISBN: 9781450331302","raw_type":"info:eu-repo/semantics/publishedVersion"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.5099999904632568}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W36234522","https://openalex.org/W2015780963","https://openalex.org/W2048944807","https://openalex.org/W2113615682","https://openalex.org/W2118638759","https://openalex.org/W2130193491","https://openalex.org/W2160367103"],"related_works":["https://openalex.org/W2544043553","https://openalex.org/W1587494897","https://openalex.org/W2169674017","https://openalex.org/W2385174725","https://openalex.org/W2188443807","https://openalex.org/W1497726515","https://openalex.org/W2129487136","https://openalex.org/W2770508556","https://openalex.org/W2073686524","https://openalex.org/W2084587871"],"abstract_inverted_index":{"Dynamic":[0],"Circuit":[1],"Specialization":[2],"(DCS)":[3],"is":[4,37,45,75],"a":[5,33,48,92,98],"technique":[6,59,74],"used":[7,91],"to":[8,23],"optimize":[9],"FPGA":[10,35,44,67,81],"applications":[11],"when":[12],"some":[13],"of":[14,29,56,64,71,108],"the":[15,43,54,57,62,72,102,106,109],"inputs,":[16],"called":[17],"parameters,":[18],"are":[19],"infrequently":[20],"changing":[21],"compared":[22],"other":[24],"inputs.":[25],"For":[26],"every":[27],"change":[28],"parameter":[30],"input":[31],"values,":[32],"specialized":[34,49],"configuration":[36],"generated":[38],"during":[39],"run":[40],"time":[41],"and":[42,86],"reconfigured":[46],"with":[47,61,101],"bitstream.":[50],"We":[51,89],"examine":[52],"how":[53],"performance":[55,70],"DCS":[58,73],"evolves":[60],"advent":[63],"newer":[65],"Xilinx":[66,80],"architectures.":[68],"The":[69],"evaluated":[76],"on":[77],"three":[78],"different":[79],"architectures:":[82],"Virtex-II":[83],"Pro,":[84],"Virtex-5":[85],"Zynq":[87],"SoC.":[88],"have":[90],"16-tap,":[93],"8-bit":[94],"FIR":[95,110],"filter":[96,103],"as":[97,105],"parameterized":[99],"design,":[100],"coefficients":[104],"parameters":[107],"design.":[111]},"counts_by_year":[{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":4},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":1}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}