{"id":"https://openalex.org/W2051428313","doi":"https://doi.org/10.1145/2660540.2661009","title":"Exploring Independent Gates in FinFET-Based Transistor Network Generation","display_name":"Exploring Independent Gates in FinFET-Based Transistor Network Generation","publication_year":2014,"publication_date":"2014-09-01","ids":{"openalex":"https://openalex.org/W2051428313","doi":"https://doi.org/10.1145/2660540.2661009","mag":"2051428313"},"language":"en","primary_location":{"id":"doi:10.1145/2660540.2661009","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2660540.2661009","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 27th Symposium on Integrated Circuits and Systems Design","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"http://guaiaca.ufpel.edu.br/handle/prefix/8604","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5031641596","display_name":"Vinicius N. Possani","orcid":"https://orcid.org/0000-0003-4334-1174"},"institutions":[{"id":"https://openalex.org/I169248161","display_name":"Universidade Federal de Pelotas","ror":"https://ror.org/05msy9z54","country_code":"BR","type":"education","lineage":["https://openalex.org/I169248161"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Vinicius N. Possani","raw_affiliation_strings":["Technology Development Center, Federal University of Pelotas, Pelotas, Brazil","Technology Development Center, Federal University of Pelotas, Pelotas, Brazil#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Technology Development Center, Federal University of Pelotas, Pelotas, Brazil","institution_ids":["https://openalex.org/I169248161"]},{"raw_affiliation_string":"Technology Development Center, Federal University of Pelotas, Pelotas, Brazil#TAB#","institution_ids":["https://openalex.org/I169248161"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5065397615","display_name":"Andr\u00e9 I. Reis","orcid":"https://orcid.org/0000-0002-3118-8160"},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Andr\u00e9 I. Reis","raw_affiliation_strings":["Institute of Informatics, Federal University of Rio Grande do Sul, Porto Alegre, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Informatics, Federal University of Rio Grande do Sul, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5090563366","display_name":"Renato P. Ribas","orcid":"https://orcid.org/0000-0002-9895-7489"},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Renato P. Ribas","raw_affiliation_strings":["Institute of Informatics, Federal University of Rio Grande do Sul, Porto Alegre, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Informatics, Federal University of Rio Grande do Sul, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5068796829","display_name":"Felipe Marques","orcid":"https://orcid.org/0000-0003-1318-9992"},"institutions":[{"id":"https://openalex.org/I169248161","display_name":"Universidade Federal de Pelotas","ror":"https://ror.org/05msy9z54","country_code":"BR","type":"education","lineage":["https://openalex.org/I169248161"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Felipe S. Marques","raw_affiliation_strings":["Technology Development Center, Federal University of Pelotas, Pelotas, Brazil","Technology Development Center, Federal University of Pelotas, Pelotas, Brazil#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Technology Development Center, Federal University of Pelotas, Pelotas, Brazil","institution_ids":["https://openalex.org/I169248161"]},{"raw_affiliation_string":"Technology Development Center, Federal University of Pelotas, Pelotas, Brazil#TAB#","institution_ids":["https://openalex.org/I169248161"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5014303947","display_name":"Leomar S. da Rosa","orcid":"https://orcid.org/0000-0002-7150-5685"},"institutions":[{"id":"https://openalex.org/I169248161","display_name":"Universidade Federal de Pelotas","ror":"https://ror.org/05msy9z54","country_code":"BR","type":"education","lineage":["https://openalex.org/I169248161"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Leomar S. da Rosa Junior","raw_affiliation_strings":["Technology Development Center, Federal University of Pelotas, Pelotas, Brazil","Technology Development Center, Federal University of Pelotas, Pelotas, Brazil#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Technology Development Center, Federal University of Pelotas, Pelotas, Brazil","institution_ids":["https://openalex.org/I169248161"]},{"raw_affiliation_string":"Technology Development Center, Federal University of Pelotas, Pelotas, Brazil#TAB#","institution_ids":["https://openalex.org/I169248161"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":"37","issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6286354064941406},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.578090250492096},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5514696836471558},{"id":"https://openalex.org/keywords/graph","display_name":"Graph","score":0.474870890378952},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.40820395946502686},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.2938004732131958},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2849116325378418},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2256186604499817},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1709354817867279},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.09603169560432434}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6286354064941406},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.578090250492096},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5514696836471558},{"id":"https://openalex.org/C132525143","wikidata":"https://www.wikidata.org/wiki/Q141488","display_name":"Graph","level":2,"score":0.474870890378952},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.40820395946502686},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.2938004732131958},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2849116325378418},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2256186604499817},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1709354817867279},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.09603169560432434}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1145/2660540.2661009","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2660540.2661009","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 27th Symposium on Integrated Circuits and Systems Design","raw_type":"proceedings-article"},{"id":"pmh:oai:guaiaca.ufpel.edu.br:prefix/8604","is_oa":true,"landing_page_url":"http://guaiaca.ufpel.edu.br/handle/prefix/8604","pdf_url":null,"source":null,"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"reponame:Reposit\u00f3rio Institucional da UFPel - Guaiaca","raw_type":"info:eu-repo/semantics/publishedVersion"},{"id":"pmh:oai:repositorio.ufpel.edu.br:prefix/8604","is_oa":true,"landing_page_url":"http://guaiaca.ufpel.edu.br:8080/handle/prefix/8604","pdf_url":null,"source":{"id":"https://openalex.org/S4377196500","display_name":"UFPEL (Universidade Federal de Pelotas)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I169248161","host_organization_name":"Universidade Federal de Pelotas","host_organization_lineage":["https://openalex.org/I169248161"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-nc-sa","license_id":"https://openalex.org/licenses/cc-by-nc-sa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"reponame:Reposit\u00f3rio Institucional da UFPEL","raw_type":"info:eu-repo/semantics/publishedVersion"}],"best_oa_location":{"id":"pmh:oai:guaiaca.ufpel.edu.br:prefix/8604","is_oa":true,"landing_page_url":"http://guaiaca.ufpel.edu.br/handle/prefix/8604","pdf_url":null,"source":null,"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"reponame:Reposit\u00f3rio Institucional da UFPel - Guaiaca","raw_type":"info:eu-repo/semantics/publishedVersion"},"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320321091","display_name":"Coordena\u00e7\u00e3o de Aperfei\u00e7oamento de Pessoal de N\u00edvel Superior","ror":"https://ror.org/00x0ma614"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1489111899","https://openalex.org/W1976597925","https://openalex.org/W2015987974","https://openalex.org/W2031298013","https://openalex.org/W2095596186","https://openalex.org/W2105874609","https://openalex.org/W2126810113","https://openalex.org/W2127587406","https://openalex.org/W2135327658","https://openalex.org/W2153865810","https://openalex.org/W2167756350","https://openalex.org/W2536886358"],"related_works":["https://openalex.org/W4391375266","https://openalex.org/W2748952813","https://openalex.org/W2390279801","https://openalex.org/W2358668433","https://openalex.org/W4396701345","https://openalex.org/W2376932109","https://openalex.org/W2001405890","https://openalex.org/W4396696052","https://openalex.org/W4402327032","https://openalex.org/W2588941787"],"abstract_inverted_index":{"This":[0,51],"paper":[1,74],"shows":[2],"that":[3,29,96],"double":[4,67],"gate":[5,68],"devices,":[6],"like":[7],"independent-gate":[8],"(IG)":[9],"FinFETs,":[10],"have":[11],"introduced":[12],"new":[13],"challenges":[14],"in":[15,35],"the":[16,22,31,86,97,102,109],"transistor":[17,113],"network":[18,49,114],"generation":[19],"step":[20],"during":[21],"logic":[23],"synthesis.":[24],"The":[25,93],"main":[26],"point":[27],"is":[28,40],"reducing":[30],"number":[32,103],"of":[33,89,104,112],"literals":[34],"a":[36,45,76],"given":[37],"Boolean":[38],"expression":[39],"not":[41,60],"enough":[42],"to":[43,63,80,84,108],"guarantee":[44],"minimum":[46],"IG":[47,91,105],"FinFET":[48],"implementation.":[50],"way,":[52],"traditional":[53,110],"factorization":[54],"methods":[55,111],"or":[56],"graph-based":[57,77],"optimizations":[58],"may":[59],"be":[61],"useful":[62],"generate":[64],"networks":[65],"for":[66],"devices.":[69],"In":[70],"this":[71,73],"sense,":[72],"presents":[75],"method":[78,99],"able":[79],"find":[81],"promising":[82],"arrangements":[83],"explore":[85],"separated":[87],"gates":[88],"each":[90],"FinFET.":[92],"experiments":[94],"demonstrate":[95],"proposed":[98],"can":[100],"reduce":[101],"FinFETs":[106],"compared":[107],"generation.":[115]},"counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2017,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}