{"id":"https://openalex.org/W2027603842","doi":"https://doi.org/10.1145/2659532.2659616","title":"Design space exploration in multi-level computing systems","display_name":"Design space exploration in multi-level computing systems","publication_year":2014,"publication_date":"2014-06-27","ids":{"openalex":"https://openalex.org/W2027603842","doi":"https://doi.org/10.1145/2659532.2659616","mag":"2027603842"},"language":"en","primary_location":{"id":"doi:10.1145/2659532.2659616","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2659532.2659616","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 15th International Conference on Computer Systems and Technologies","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5053527505","display_name":"Valery Sklyarov","orcid":"https://orcid.org/0000-0003-0349-8329"},"institutions":[{"id":"https://openalex.org/I60858718","display_name":"University of Aveiro","ror":"https://ror.org/00nt41z93","country_code":"PT","type":"education","lineage":["https://openalex.org/I60858718"]}],"countries":["PT"],"is_corresponding":true,"raw_author_name":"Valery Sklyarov","raw_affiliation_strings":["University of Aveiro, Portugal"],"affiliations":[{"raw_affiliation_string":"University of Aveiro, Portugal","institution_ids":["https://openalex.org/I60858718"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5085215501","display_name":"Iouliia Skliarova","orcid":"https://orcid.org/0000-0002-6684-9416"},"institutions":[{"id":"https://openalex.org/I60858718","display_name":"University of Aveiro","ror":"https://ror.org/00nt41z93","country_code":"PT","type":"education","lineage":["https://openalex.org/I60858718"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"Iouliia Skliarova","raw_affiliation_strings":["University of Aveiro, Portugal"],"affiliations":[{"raw_affiliation_string":"University of Aveiro, Portugal","institution_ids":["https://openalex.org/I60858718"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5039688642","display_name":"Jo\u00e3o Silva","orcid":"https://orcid.org/0000-0001-5535-754X"},"institutions":[{"id":"https://openalex.org/I60858718","display_name":"University of Aveiro","ror":"https://ror.org/00nt41z93","country_code":"PT","type":"education","lineage":["https://openalex.org/I60858718"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"Jo\u00e3o Silva","raw_affiliation_strings":["University of Aveiro, Portugal"],"affiliations":[{"raw_affiliation_string":"University of Aveiro, Portugal","institution_ids":["https://openalex.org/I60858718"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5069958724","display_name":"Alexander Sudnitson","orcid":null},"institutions":[{"id":"https://openalex.org/I111112146","display_name":"Tallinn University of Technology","ror":"https://ror.org/0443cwa12","country_code":"EE","type":"education","lineage":["https://openalex.org/I111112146"]}],"countries":["EE"],"is_corresponding":false,"raw_author_name":"Alexander Sudnitson","raw_affiliation_strings":["Tallinn University of Technology, Estonia","Tallinn University of Technology , Estonia"],"affiliations":[{"raw_affiliation_string":"Tallinn University of Technology, Estonia","institution_ids":["https://openalex.org/I111112146"]},{"raw_affiliation_string":"Tallinn University of Technology , Estonia","institution_ids":["https://openalex.org/I111112146"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5053527505"],"corresponding_institution_ids":["https://openalex.org/I60858718"],"apc_list":null,"apc_paid":null,"fwci":0.6301,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.69260933,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"40","last_page":"47"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13292","display_name":"Embedded Systems and FPGA Applications","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9865000247955322,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.8160103559494019},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7192902565002441},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6843945980072021},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.5589404702186584},{"id":"https://openalex.org/keywords/host","display_name":"Host (biology)","score":0.5436626076698303},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.49474427103996277},{"id":"https://openalex.org/keywords/video-graphics-array","display_name":"Video Graphics Array","score":0.45470553636550903},{"id":"https://openalex.org/keywords/programmable-logic-array","display_name":"Programmable logic array","score":0.43885892629623413},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.43085652589797974},{"id":"https://openalex.org/keywords/simple-programmable-logic-device","display_name":"Simple programmable logic device","score":0.41666799783706665},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4039573669433594},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.3652859628200531},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.29107868671417236},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.20459353923797607},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.10605263710021973}],"concepts":[{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.8160103559494019},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7192902565002441},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6843945980072021},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.5589404702186584},{"id":"https://openalex.org/C126831891","wikidata":"https://www.wikidata.org/wiki/Q221673","display_name":"Host (biology)","level":2,"score":0.5436626076698303},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.49474427103996277},{"id":"https://openalex.org/C139983466","wikidata":"https://www.wikidata.org/wiki/Q17194","display_name":"Video Graphics Array","level":3,"score":0.45470553636550903},{"id":"https://openalex.org/C182322920","wikidata":"https://www.wikidata.org/wiki/Q2112217","display_name":"Programmable logic array","level":3,"score":0.43885892629623413},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.43085652589797974},{"id":"https://openalex.org/C34370810","wikidata":"https://www.wikidata.org/wiki/Q3961319","display_name":"Simple programmable logic device","level":5,"score":0.41666799783706665},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4039573669433594},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.3652859628200531},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.29107868671417236},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.20459353923797607},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.10605263710021973},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C18903297","wikidata":"https://www.wikidata.org/wiki/Q7150","display_name":"Ecology","level":1,"score":0.0},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2659532.2659616","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2659532.2659616","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 15th International Conference on Computer Systems and Technologies","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320320300","display_name":"European Commission","ror":"https://ror.org/00k4n6c32"},{"id":"https://openalex.org/F4320321018","display_name":"Eesti Teadusfondi","ror":"https://ror.org/00jjeja18"},{"id":"https://openalex.org/F4320334779","display_name":"Funda\u00e7\u00e3o para a Ci\u00eancia e a Tecnologia","ror":"https://ror.org/00snfqn58"},{"id":"https://openalex.org/F4320335322","display_name":"European Regional Development Fund","ror":"https://ror.org/00k4n6c32"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W588038372","https://openalex.org/W1989584178","https://openalex.org/W1992337792","https://openalex.org/W2076089313","https://openalex.org/W2098424698"],"related_works":["https://openalex.org/W2243781098","https://openalex.org/W2187918628","https://openalex.org/W1607849496","https://openalex.org/W1512285683","https://openalex.org/W2197466303","https://openalex.org/W2139569078","https://openalex.org/W2151236218","https://openalex.org/W4234601000","https://openalex.org/W2368888192","https://openalex.org/W2147419146"],"abstract_inverted_index":{"The":[0,32,126],"paper":[1,127],"is":[2],"dedicated":[3],"to":[4,40,68,71,76],"the":[5,29,58,72,78,81,90,98,129,134],"design":[6],"space":[7],"exploration":[8],"for":[9,114,139],"Xilinx":[10],"devices":[11,117],"from":[12,80],"Zynq-7000":[13],"family":[14],"with":[15,57],"such":[16,116,141],"architecture":[17],"that":[18,43,65],"includes":[19],"a":[20,25,45,49],"dual-core":[21],"processing":[22,92],"system":[23,36,52,93,142],"and":[24,53,75,94,121,137],"programmable":[26,100],"logic":[27],"on":[28],"same":[30],"microchip.":[31],"developed":[33,135],"multi-level":[34],"computing":[35],"enables":[37],"three":[38],"subsystems":[39],"be":[41],"combined":[42],"are:":[44],"personal":[46],"host":[47,59],"computer,":[48],"Zynq-based":[50],"hardware/software":[51],"peripheral":[54,112],"devices.":[55],"Interactions":[56],"computer":[60],"are":[61,66],"provided":[62],"through":[63],"files":[64],"used":[67],"supply":[69],"data":[70],"Zynq":[73,82,91,99],"device":[74],"get":[77],"results":[79,130],"device.":[83],"For":[84],"interactions":[85],"between":[86],"software":[87],"running":[88],"in":[89,97,143],"hardware":[95],"implemented":[96],"logic,":[101],"different":[102],"types":[103],"of":[104,111,131,133],"interfaces":[105],"have":[106,123],"been":[107,124],"supported.":[108],"A":[109],"number":[110],"modules":[113],"using":[115,140],"as":[118],"VGA":[119],"monitors":[120],"keypads":[122],"designed.":[125],"reports":[128],"integration":[132],"components":[136],"proposals":[138],"practical":[144],"applications.":[145]},"counts_by_year":[{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1}],"updated_date":"2026-04-21T08:09:41.155169","created_date":"2025-10-10T00:00:00"}
