{"id":"https://openalex.org/W2129107917","doi":"https://doi.org/10.1145/2656106.2656121","title":"EnVM","display_name":"EnVM","publication_year":2014,"publication_date":"2014-10-12","ids":{"openalex":"https://openalex.org/W2129107917","doi":"https://doi.org/10.1145/2656106.2656121","mag":"2129107917"},"language":"en","primary_location":{"id":"doi:10.1145/2656106.2656121","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2656106.2656121","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2014 International Conference on Compilers, Architecture and Synthesis for Embedded Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5023670626","display_name":"Pooja Roy","orcid":null},"institutions":[{"id":"https://openalex.org/I165932596","display_name":"National University of Singapore","ror":"https://ror.org/01tgyzw49","country_code":"SG","type":"education","lineage":["https://openalex.org/I165932596"]}],"countries":["SG"],"is_corresponding":true,"raw_author_name":"Pooja Roy","raw_affiliation_strings":["National University of Singapore","School of Computing, National University of Singapore,"],"affiliations":[{"raw_affiliation_string":"National University of Singapore","institution_ids":["https://openalex.org/I165932596"]},{"raw_affiliation_string":"School of Computing, National University of Singapore,","institution_ids":["https://openalex.org/I165932596"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5056188675","display_name":"Manmohan Manoharan","orcid":null},"institutions":[{"id":"https://openalex.org/I165932596","display_name":"National University of Singapore","ror":"https://ror.org/01tgyzw49","country_code":"SG","type":"education","lineage":["https://openalex.org/I165932596"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Manmohan Manoharan","raw_affiliation_strings":["National University of Singapore","School of Computing, National University of Singapore,"],"affiliations":[{"raw_affiliation_string":"National University of Singapore","institution_ids":["https://openalex.org/I165932596"]},{"raw_affiliation_string":"School of Computing, National University of Singapore,","institution_ids":["https://openalex.org/I165932596"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5023989495","display_name":"Weng\u2010Fai Wong","orcid":"https://orcid.org/0000-0002-4281-2053"},"institutions":[{"id":"https://openalex.org/I165932596","display_name":"National University of Singapore","ror":"https://ror.org/01tgyzw49","country_code":"SG","type":"education","lineage":["https://openalex.org/I165932596"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Weng Fai Wong","raw_affiliation_strings":["National University of Singapore","School of Computing, National University of Singapore,"],"affiliations":[{"raw_affiliation_string":"National University of Singapore","institution_ids":["https://openalex.org/I165932596"]},{"raw_affiliation_string":"School of Computing, National University of Singapore,","institution_ids":["https://openalex.org/I165932596"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5023670626"],"corresponding_institution_ids":["https://openalex.org/I165932596"],"apc_list":null,"apc_paid":null,"fwci":0.613,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.70906511,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"10"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8013509511947632},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.590045154094696},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.5201842784881592},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5186452269554138},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.477588415145874},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.47433561086654663},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.44612401723861694},{"id":"https://openalex.org/keywords/cache-only-memory-architecture","display_name":"Cache-only memory architecture","score":0.42585262656211853},{"id":"https://openalex.org/keywords/memory-map","display_name":"Memory map","score":0.42197537422180176},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.40459728240966797},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.34251031279563904},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.34078359603881836},{"id":"https://openalex.org/keywords/cache-coloring","display_name":"Cache coloring","score":0.2809171974658966},{"id":"https://openalex.org/keywords/shared-memory","display_name":"Shared memory","score":0.21587106585502625}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8013509511947632},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.590045154094696},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.5201842784881592},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5186452269554138},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.477588415145874},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.47433561086654663},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.44612401723861694},{"id":"https://openalex.org/C3720319","wikidata":"https://www.wikidata.org/wiki/Q5015937","display_name":"Cache-only memory architecture","level":5,"score":0.42585262656211853},{"id":"https://openalex.org/C74426580","wikidata":"https://www.wikidata.org/wiki/Q719484","display_name":"Memory map","level":3,"score":0.42197537422180176},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.40459728240966797},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.34251031279563904},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.34078359603881836},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.2809171974658966},{"id":"https://openalex.org/C133875982","wikidata":"https://www.wikidata.org/wiki/Q764810","display_name":"Shared memory","level":2,"score":0.21587106585502625}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2656106.2656121","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2656106.2656121","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2014 International Conference on Compilers, Architecture and Synthesis for Embedded Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8999999761581421}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":25,"referenced_works":["https://openalex.org/W1964044001","https://openalex.org/W1973459854","https://openalex.org/W1989660200","https://openalex.org/W2010202670","https://openalex.org/W2017722158","https://openalex.org/W2047379549","https://openalex.org/W2060673228","https://openalex.org/W2072730350","https://openalex.org/W2080739090","https://openalex.org/W2084007230","https://openalex.org/W2096259250","https://openalex.org/W2108048675","https://openalex.org/W2115971347","https://openalex.org/W2116826022","https://openalex.org/W2131734025","https://openalex.org/W2132389101","https://openalex.org/W2138146350","https://openalex.org/W2142276919","https://openalex.org/W2150662965","https://openalex.org/W2153716894","https://openalex.org/W2156159026","https://openalex.org/W3124619212","https://openalex.org/W3137284226","https://openalex.org/W4205643817","https://openalex.org/W4231325241"],"related_works":["https://openalex.org/W254684032","https://openalex.org/W2934889147","https://openalex.org/W1554378476","https://openalex.org/W3021597805","https://openalex.org/W2999459628","https://openalex.org/W2123199776","https://openalex.org/W207100770","https://openalex.org/W4248614727","https://openalex.org/W3048967625","https://openalex.org/W2043352873"],"abstract_inverted_index":{"Virtual":[0],"memory":[1,6,10,31,64,131],"is":[2,43,65,71,119],"optimized":[3],"for":[4,87],"SRAM-based":[5],"devices":[7],"in":[8,165],"which":[9,61],"accesses":[11,21],"are":[12,22,35,50,82,101],"symmetric,":[13],"i.e.,":[14],"the":[15,26,62,93,96,114,117,130,144],"latency":[16],"of":[17,28,85,95,129,154],"read":[18],"and":[19,37,57,79,106,139],"write":[20,55,59],"similar.":[23],"Unfortunately,":[24],"with":[25,104,110],"emergence":[27],"newer":[29],"non-volatile":[30],"(NVM)":[32],"technologies":[33],"that":[34,75],"denser":[36],"more":[38],"energy":[39],"efficient,":[40],"this":[41],"assumption":[42],"no":[44],"longer":[45],"valid.":[46],"For":[47],"example,":[48],"STT-RAMs":[49],"known":[51],"to":[52,123,137,159],"have":[53],"high":[54],"latencies":[56],"limited":[58],"endurance":[60],"virtual":[63],"unaware":[66],"of.":[67],"A":[68],"popular":[69],"architecture":[70],"a":[72,83],"hybrid":[73],"cache":[74,118],"uses":[76],"both":[77],"SRAM":[78],"NVM.":[80],"There":[81],"number":[84],"proposals":[86,100],"such":[88,133],"architectures":[89],"at":[90,113,126,151],"nearly":[91],"all":[92],"levels":[94,128,153],"cache.":[97],"However,":[98],"these":[99],"often":[102],"self-contained":[103],"monitoring":[105],"management":[107,145],"schemes":[108],"implemented":[109,147],"special":[111],"hardware":[112],"level":[115],"where":[116],"deployed.":[120],"With":[121],"moves":[122],"use":[124],"NVM":[125],"several":[127],"hierarchy,":[132],"solutions":[134],"may":[135,157],"lead":[136,158],"duplication":[138],"higher":[140],"overheads.":[141],"Worse,":[142],"because":[143],"algorithms":[146],"can":[148],"be":[149],"different":[150,152],"memory,":[155],"it":[156],"negative":[160],"interference":[161],"between":[162],"them":[163],"resulting":[164],"impaired":[166],"efficiency.":[167]},"counts_by_year":[{"year":2015,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2016-06-24T00:00:00"}