{"id":"https://openalex.org/W2103431534","doi":"https://doi.org/10.1145/2656075.2656081","title":"Code generation from a domain-specific language for C-based HLS of hardware accelerators","display_name":"Code generation from a domain-specific language for C-based HLS of hardware accelerators","publication_year":2014,"publication_date":"2014-10-07","ids":{"openalex":"https://openalex.org/W2103431534","doi":"https://doi.org/10.1145/2656075.2656081","mag":"2103431534"},"language":"en","primary_location":{"id":"doi:10.1145/2656075.2656081","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2656075.2656081","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5051274212","display_name":"Oliver Reiche","orcid":"https://orcid.org/0000-0002-5125-4508"},"institutions":[{"id":"https://openalex.org/I181369854","display_name":"Friedrich-Alexander-Universit\u00e4t Erlangen-N\u00fcrnberg","ror":"https://ror.org/00f7hpc57","country_code":"DE","type":"education","lineage":["https://openalex.org/I181369854"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Oliver Reiche","raw_affiliation_strings":["Friedrich-Alexander University Erlangen-N\u00fcrnberg (FAU), Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Friedrich-Alexander University Erlangen-N\u00fcrnberg (FAU), Germany","institution_ids":["https://openalex.org/I181369854"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111887854","display_name":"Moritz Schmid","orcid":null},"institutions":[{"id":"https://openalex.org/I181369854","display_name":"Friedrich-Alexander-Universit\u00e4t Erlangen-N\u00fcrnberg","ror":"https://ror.org/00f7hpc57","country_code":"DE","type":"education","lineage":["https://openalex.org/I181369854"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Moritz Schmid","raw_affiliation_strings":["Friedrich-Alexander University Erlangen-N\u00fcrnberg (FAU), Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Friedrich-Alexander University Erlangen-N\u00fcrnberg (FAU), Germany","institution_ids":["https://openalex.org/I181369854"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5072039340","display_name":"Frank Hannig","orcid":"https://orcid.org/0000-0003-3663-6484"},"institutions":[{"id":"https://openalex.org/I181369854","display_name":"Friedrich-Alexander-Universit\u00e4t Erlangen-N\u00fcrnberg","ror":"https://ror.org/00f7hpc57","country_code":"DE","type":"education","lineage":["https://openalex.org/I181369854"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Frank Hannig","raw_affiliation_strings":["Friedrich-Alexander University Erlangen-N\u00fcrnberg (FAU), Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Friedrich-Alexander University Erlangen-N\u00fcrnberg (FAU), Germany","institution_ids":["https://openalex.org/I181369854"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5024954324","display_name":"Richard Membarth","orcid":"https://orcid.org/0000-0002-9979-7579"},"institutions":[{"id":"https://openalex.org/I4210094487","display_name":"Intel (Germany)","ror":"https://ror.org/00m2x0g47","country_code":"DE","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210094487"]},{"id":"https://openalex.org/I91712215","display_name":"Saarland University","ror":"https://ror.org/01jdpyv68","country_code":"DE","type":"education","lineage":["https://openalex.org/I91712215"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Richard Membarth","raw_affiliation_strings":["Saarland University, Germany","Intel Visual Computing Institute, Saarland University, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Saarland University, Germany","institution_ids":["https://openalex.org/I91712215"]},{"raw_affiliation_string":"Intel Visual Computing Institute, Saarland University, Germany","institution_ids":["https://openalex.org/I4210094487","https://openalex.org/I91712215"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5076672029","display_name":"J\u00fcrgen Teich","orcid":"https://orcid.org/0000-0001-6285-5862"},"institutions":[{"id":"https://openalex.org/I181369854","display_name":"Friedrich-Alexander-Universit\u00e4t Erlangen-N\u00fcrnberg","ror":"https://ror.org/00f7hpc57","country_code":"DE","type":"education","lineage":["https://openalex.org/I181369854"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"J\u00fcrgen Teich","raw_affiliation_strings":["Friedrich-Alexander University Erlangen-N\u00fcrnberg (FAU), Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Friedrich-Alexander University Erlangen-N\u00fcrnberg (FAU), Germany","institution_ids":["https://openalex.org/I181369854"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":5.2398,"has_fulltext":false,"cited_by_count":42,"citation_normalized_percentile":{"value":0.96384644,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":100},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"10"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7686521410942078},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.766051173210144},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6016847491264343},{"id":"https://openalex.org/keywords/domain","display_name":"Domain (mathematical analysis)","score":0.5590300559997559},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5316569805145264},{"id":"https://openalex.org/keywords/code-generation","display_name":"Code generation","score":0.5298792123794556},{"id":"https://openalex.org/keywords/code","display_name":"Code (set theory)","score":0.5016796588897705},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.4522448778152466},{"id":"https://openalex.org/keywords/domain-specific-language","display_name":"Domain-specific language","score":0.43720555305480957},{"id":"https://openalex.org/keywords/hardware-acceleration","display_name":"Hardware acceleration","score":0.41905510425567627},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3536749482154846},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.21153035759925842},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.1622009575366974}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7686521410942078},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.766051173210144},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6016847491264343},{"id":"https://openalex.org/C36503486","wikidata":"https://www.wikidata.org/wiki/Q11235244","display_name":"Domain (mathematical analysis)","level":2,"score":0.5590300559997559},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5316569805145264},{"id":"https://openalex.org/C133162039","wikidata":"https://www.wikidata.org/wiki/Q1061077","display_name":"Code generation","level":3,"score":0.5298792123794556},{"id":"https://openalex.org/C2776760102","wikidata":"https://www.wikidata.org/wiki/Q5139990","display_name":"Code (set theory)","level":3,"score":0.5016796588897705},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.4522448778152466},{"id":"https://openalex.org/C135257023","wikidata":"https://www.wikidata.org/wiki/Q691358","display_name":"Domain-specific language","level":2,"score":0.43720555305480957},{"id":"https://openalex.org/C13164978","wikidata":"https://www.wikidata.org/wiki/Q600158","display_name":"Hardware acceleration","level":3,"score":0.41905510425567627},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3536749482154846},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.21153035759925842},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.1622009575366974},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.0},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2656075.2656081","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2656075.2656081","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8399999737739563,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320309480","display_name":"Nvidia","ror":"https://ror.org/03jdj4y14"},{"id":"https://openalex.org/F4320320879","display_name":"Deutsche Forschungsgemeinschaft","ror":"https://ror.org/018mejw64"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1499225944","https://openalex.org/W1885706698","https://openalex.org/W1980208272","https://openalex.org/W1999819296","https://openalex.org/W2018055497","https://openalex.org/W2037089143","https://openalex.org/W2054214690","https://openalex.org/W2111308925","https://openalex.org/W2127699991","https://openalex.org/W2154237975","https://openalex.org/W2155942864","https://openalex.org/W2191327475","https://openalex.org/W2493328864","https://openalex.org/W3210232381","https://openalex.org/W6687987274","https://openalex.org/W6803376173"],"related_works":["https://openalex.org/W1612076744","https://openalex.org/W2152074211","https://openalex.org/W2126857316","https://openalex.org/W2129019972","https://openalex.org/W3164085601","https://openalex.org/W1522032972","https://openalex.org/W2139962137","https://openalex.org/W2113308450","https://openalex.org/W2340647897","https://openalex.org/W3139915793"],"abstract_inverted_index":{"As":[0],"today's":[1],"computer":[2],"architectures":[3],"are":[4],"becoming":[5],"more":[6,8],"and":[7,21,57],"heterogeneous,":[9],"a":[10,45],"plethora":[11],"of":[12,35,51],"options":[13],"including":[14],"CPUs,":[15],"GPUs,":[16],"DSPs,":[17],"reconfigurable":[18],"logic":[19],"(FPGAs),":[20],"other":[22],"application-specific":[23],"processors":[24],"come":[25],"into":[26],"consideration":[27],"for":[28,61],"close-to-sensor":[29],"processing.":[30],"Especially,":[31],"in":[32],"the":[33],"domain":[34],"image":[36],"processing":[37],"on":[38],"mobile":[39],"devices,":[40],"among":[41],"numerous":[42],"design":[43],"challenges,":[44],"very":[46],"stringent":[47],"energy":[48],"budget":[49],"is":[50],"utmost":[52],"importance,":[53],"making":[54],"embedded":[55],"GPUs":[56],"FPGAs":[58],"ideal":[59],"targets":[60],"implementation.":[62]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":4},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":6},{"year":2016,"cited_by_count":13},{"year":2015,"cited_by_count":6},{"year":2014,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}