{"id":"https://openalex.org/W2061917031","doi":"https://doi.org/10.1145/2641361.2641378","title":"Customisable architectures for the set covering problem","display_name":"Customisable architectures for the set covering problem","publication_year":2013,"publication_date":"2013-12-18","ids":{"openalex":"https://openalex.org/W2061917031","doi":"https://doi.org/10.1145/2641361.2641378","mag":"2061917031"},"language":"en","primary_location":{"id":"doi:10.1145/2641361.2641378","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2641361.2641378","pdf_url":null,"source":{"id":"https://openalex.org/S4210193905","display_name":"ACM SIGARCH Computer Architecture News","issn_l":"0163-5964","issn":["0163-5964","1943-5851"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320740","host_organization_name":"ACM SIGARCH","host_organization_lineage":["https://openalex.org/P4310320740"],"host_organization_lineage_names":["ACM SIGARCH"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM SIGARCH Computer Architecture News","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5057083854","display_name":"Liucheng Guo","orcid":"https://orcid.org/0009-0008-9419-4075"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Liucheng Guo","raw_affiliation_strings":["Imperial College London, London, U.K","Imperial College London, London, U.K#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Imperial College London, London, U.K","institution_ids":["https://openalex.org/I47508984"]},{"raw_affiliation_string":"Imperial College London, London, U.K#TAB#","institution_ids":["https://openalex.org/I47508984"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081452934","display_name":"David B. Thomas","orcid":"https://orcid.org/0000-0002-9671-0917"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"David B. Thomas","raw_affiliation_strings":["Imperial College London, London, U.K","Imperial College London, London, U.K#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Imperial College London, London, U.K","institution_ids":["https://openalex.org/I47508984"]},{"raw_affiliation_string":"Imperial College London, London, U.K#TAB#","institution_ids":["https://openalex.org/I47508984"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5057940557","display_name":"Wayne Luk","orcid":"https://orcid.org/0000-0002-6750-927X"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Wayne Luk","raw_affiliation_strings":["Imperial College London, London, U.K","Imperial College London, London, U.K#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Imperial College London, London, U.K","institution_ids":["https://openalex.org/I47508984"]},{"raw_affiliation_string":"Imperial College London, London, U.K#TAB#","institution_ids":["https://openalex.org/I47508984"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I47508984"],"apc_list":null,"apc_paid":null,"fwci":2.1801,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.87753476,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"41","issue":"5","first_page":"101","last_page":"106"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11269","display_name":"Algorithms and Data Compression","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8125793933868408},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.752252459526062},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.6188960671424866},{"id":"https://openalex.org/keywords/implementation","display_name":"Implementation","score":0.6113715171813965},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6055334806442261},{"id":"https://openalex.org/keywords/parallelism","display_name":"Parallelism (grammar)","score":0.577964186668396},{"id":"https://openalex.org/keywords/genetic-algorithm","display_name":"Genetic algorithm","score":0.5241844058036804},{"id":"https://openalex.org/keywords/pipeline-transport","display_name":"Pipeline transport","score":0.49843597412109375},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.4673866033554077},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.40153953433036804},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.37973907589912415},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.34288498759269714},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.1469358205795288},{"id":"https://openalex.org/keywords/machine-learning","display_name":"Machine learning","score":0.07325044274330139}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8125793933868408},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.752252459526062},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.6188960671424866},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.6113715171813965},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6055334806442261},{"id":"https://openalex.org/C2781172179","wikidata":"https://www.wikidata.org/wiki/Q853109","display_name":"Parallelism (grammar)","level":2,"score":0.577964186668396},{"id":"https://openalex.org/C8880873","wikidata":"https://www.wikidata.org/wiki/Q187787","display_name":"Genetic algorithm","level":2,"score":0.5241844058036804},{"id":"https://openalex.org/C175309249","wikidata":"https://www.wikidata.org/wiki/Q725864","display_name":"Pipeline transport","level":2,"score":0.49843597412109375},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.4673866033554077},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.40153953433036804},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.37973907589912415},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.34288498759269714},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.1469358205795288},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.07325044274330139},{"id":"https://openalex.org/C87717796","wikidata":"https://www.wikidata.org/wiki/Q146326","display_name":"Environmental engineering","level":1,"score":0.0},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2641361.2641378","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2641361.2641378","pdf_url":null,"source":{"id":"https://openalex.org/S4210193905","display_name":"ACM SIGARCH Computer Architecture News","issn_l":"0163-5964","issn":["0163-5964","1943-5851"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320740","host_organization_name":"ACM SIGARCH","host_organization_lineage":["https://openalex.org/P4310320740"],"host_organization_lineage_names":["ACM SIGARCH"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM SIGARCH Computer Architecture News","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W8638668","https://openalex.org/W1539971630","https://openalex.org/W1587248790","https://openalex.org/W1793406760","https://openalex.org/W1925894136","https://openalex.org/W1997358129","https://openalex.org/W2104748507","https://openalex.org/W2115294662","https://openalex.org/W2119206785","https://openalex.org/W2142962681","https://openalex.org/W2150405043","https://openalex.org/W2157054705","https://openalex.org/W2159712833","https://openalex.org/W2159731849","https://openalex.org/W2163916557","https://openalex.org/W4248500376"],"related_works":["https://openalex.org/W2120447654","https://openalex.org/W2977179488","https://openalex.org/W2144453115","https://openalex.org/W2128223750","https://openalex.org/W4238532390","https://openalex.org/W2188872161","https://openalex.org/W2002978035","https://openalex.org/W2961779879","https://openalex.org/W797688974","https://openalex.org/W2025467172"],"abstract_inverted_index":{"This":[0],"paper":[1],"proposes":[2],"novel":[3],"customisable":[4],"streaming":[5],"architectures":[6],"for":[7],"the":[8,48,57,66],"NP-hard":[9],"set":[10],"covering":[11],"problem.":[12],"Our":[13],"approach":[14],"covers":[15],"both":[16],"exhaustive":[17,58],"and":[18,24,32,63],"genetic":[19,67],"algorithms,":[20],"supporting":[21],"coarse-grain":[22],"parallelism":[23],"deep":[25],"pipelines":[26],"while":[27],"allowing":[28,82],"trade-offs":[29],"between":[30],"performance":[31],"resource":[33],"usage.":[34],"Experiments":[35],"targeting":[36],"Maxeler":[37],"systems":[38],"show":[39],"that":[40,64],"our":[41,73],"FPGA-based":[42],"designs":[43],"are":[44,75],"more":[45,76],"effective":[46],"than":[47,78],"corresponding":[49],"multicore":[50],"software":[51],"versions.":[52],"The":[53],"speed":[54],"up":[55],"of":[56,65],"algorithm":[59,68],"exceeds":[60,69],"250":[61],"times,":[62],"60":[70],"times.":[71],"Meanwhile,":[72],"implementations":[74],"flexible":[77],"other":[79],"FPGA":[80],"solutions,":[81],"users":[83],"to":[84],"customise":[85],"parameters":[86],"at":[87],"run":[88],"time":[89],"without":[90],"recompilation.":[91]},"counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":1}],"updated_date":"2026-05-21T06:26:12.895304","created_date":"2025-10-10T00:00:00"}