{"id":"https://openalex.org/W1994185234","doi":"https://doi.org/10.1145/2632218","title":"Deadline-Constrained Clustered Scheduling for VLIW Architectures using Power-Gated Register Files","display_name":"Deadline-Constrained Clustered Scheduling for VLIW Architectures using Power-Gated Register Files","publication_year":2014,"publication_date":"2014-06-01","ids":{"openalex":"https://openalex.org/W1994185234","doi":"https://doi.org/10.1145/2632218","mag":"1994185234"},"language":"en","primary_location":{"id":"doi:10.1145/2632218","is_oa":true,"landing_page_url":"https://doi.org/10.1145/2632218","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/2632218","source":{"id":"https://openalex.org/S26056741","display_name":"ACM Transactions on Architecture and Code Optimization","issn_l":"1544-3566","issn":["1544-3566","1544-3973"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Architecture and Code Optimization","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"bronze","oa_url":"https://dl.acm.org/doi/pdf/10.1145/2632218","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101606301","display_name":"Zhibin Liang","orcid":"https://orcid.org/0000-0001-5293-3687"},"institutions":[{"id":"https://openalex.org/I162868743","display_name":"Tianjin University","ror":"https://ror.org/012tb2g32","country_code":"CN","type":"education","lineage":["https://openalex.org/I162868743"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Zhibin Liang","raw_affiliation_strings":["Tianjin University, People's Republic of China"],"affiliations":[{"raw_affiliation_string":"Tianjin University, People's Republic of China","institution_ids":["https://openalex.org/I162868743"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100441535","display_name":"Wei Zhang","orcid":"https://orcid.org/0000-0001-9405-447X"},"institutions":[{"id":"https://openalex.org/I162868743","display_name":"Tianjin University","ror":"https://ror.org/012tb2g32","country_code":"CN","type":"education","lineage":["https://openalex.org/I162868743"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Wei Zhang","raw_affiliation_strings":["Tianjin University, People's Republic of China"],"affiliations":[{"raw_affiliation_string":"Tianjin University, People's Republic of China","institution_ids":["https://openalex.org/I162868743"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5046935164","display_name":"Yung-Cheng Ma","orcid":"https://orcid.org/0000-0002-8430-3871"},"institutions":[{"id":"https://openalex.org/I173093425","display_name":"Chang Gung University","ror":"https://ror.org/00d80zx46","country_code":"TW","type":"education","lineage":["https://openalex.org/I173093425"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yung-Cheng Ma","raw_affiliation_strings":["Chang-Gung University, Taoyuan, Taiwan"],"affiliations":[{"raw_affiliation_string":"Chang-Gung University, Taoyuan, Taiwan","institution_ids":["https://openalex.org/I173093425"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5101606301"],"corresponding_institution_ids":["https://openalex.org/I162868743"],"apc_list":null,"apc_paid":null,"fwci":0.3065,"has_fulltext":true,"cited_by_count":2,"citation_normalized_percentile":{"value":0.56599255,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"11","issue":"2","first_page":"1","last_page":"26"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/very-long-instruction-word","display_name":"Very long instruction word","score":0.9457554817199707},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.9221561551094055},{"id":"https://openalex.org/keywords/instruction-scheduling","display_name":"Instruction scheduling","score":0.6202714443206787},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5933791995048523},{"id":"https://openalex.org/keywords/register-allocation","display_name":"Register allocation","score":0.5491417646408081},{"id":"https://openalex.org/keywords/register-file","display_name":"Register file","score":0.5117313861846924},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.5094717144966125},{"id":"https://openalex.org/keywords/efficient-energy-use","display_name":"Efficient energy use","score":0.48571544885635376},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.4353976547718048},{"id":"https://openalex.org/keywords/digital-signal-processor","display_name":"Digital signal processor","score":0.42277970910072327},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.42180556058883667},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3317522406578064},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.3270307779312134},{"id":"https://openalex.org/keywords/dynamic-priority-scheduling","display_name":"Dynamic priority scheduling","score":0.17363616824150085},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.16907885670661926},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.11243048310279846},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.09411779046058655},{"id":"https://openalex.org/keywords/rate-monotonic-scheduling","display_name":"Rate-monotonic scheduling","score":0.0846552848815918}],"concepts":[{"id":"https://openalex.org/C170595534","wikidata":"https://www.wikidata.org/wiki/Q249743","display_name":"Very long instruction word","level":2,"score":0.9457554817199707},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.9221561551094055},{"id":"https://openalex.org/C73564150","wikidata":"https://www.wikidata.org/wiki/Q11417093","display_name":"Instruction scheduling","level":5,"score":0.6202714443206787},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5933791995048523},{"id":"https://openalex.org/C128916667","wikidata":"https://www.wikidata.org/wiki/Q1343660","display_name":"Register allocation","level":3,"score":0.5491417646408081},{"id":"https://openalex.org/C117280010","wikidata":"https://www.wikidata.org/wiki/Q180944","display_name":"Register file","level":3,"score":0.5117313861846924},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.5094717144966125},{"id":"https://openalex.org/C2742236","wikidata":"https://www.wikidata.org/wiki/Q924713","display_name":"Efficient energy use","level":2,"score":0.48571544885635376},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.4353976547718048},{"id":"https://openalex.org/C161611012","wikidata":"https://www.wikidata.org/wiki/Q106370","display_name":"Digital signal processor","level":3,"score":0.42277970910072327},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.42180556058883667},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3317522406578064},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.3270307779312134},{"id":"https://openalex.org/C107568181","wikidata":"https://www.wikidata.org/wiki/Q5319000","display_name":"Dynamic priority scheduling","level":3,"score":0.17363616824150085},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.16907885670661926},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.11243048310279846},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.09411779046058655},{"id":"https://openalex.org/C127456818","wikidata":"https://www.wikidata.org/wiki/Q238879","display_name":"Rate-monotonic scheduling","level":4,"score":0.0846552848815918},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C68387754","wikidata":"https://www.wikidata.org/wiki/Q7271585","display_name":"Schedule","level":2,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2632218","is_oa":true,"landing_page_url":"https://doi.org/10.1145/2632218","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/2632218","source":{"id":"https://openalex.org/S26056741","display_name":"ACM Transactions on Architecture and Code Optimization","issn_l":"1544-3566","issn":["1544-3566","1544-3973"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Architecture and Code Optimization","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1145/2632218","is_oa":true,"landing_page_url":"https://doi.org/10.1145/2632218","pdf_url":"https://dl.acm.org/doi/pdf/10.1145/2632218","source":{"id":"https://openalex.org/S26056741","display_name":"ACM Transactions on Architecture and Code Optimization","issn_l":"1544-3566","issn":["1544-3566","1544-3973"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Architecture and Code Optimization","raw_type":"journal-article"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.8999999761581421,"display_name":"Affordable and clean energy"}],"awards":[{"id":"https://openalex.org/G5123070411","display_name":null,"funder_award_id":"BMRPB88","funder_id":"https://openalex.org/F4320321524","funder_display_name":"Chang Gung University"}],"funders":[{"id":"https://openalex.org/F4320321524","display_name":"Chang Gung University","ror":"https://ror.org/00d80zx46"}],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W1994185234.pdf","grobid_xml":"https://content.openalex.org/works/W1994185234.grobid-xml"},"referenced_works_count":34,"referenced_works":["https://openalex.org/W10297790","https://openalex.org/W1507039213","https://openalex.org/W1686420892","https://openalex.org/W1982824763","https://openalex.org/W1985856855","https://openalex.org/W2011039300","https://openalex.org/W2018298029","https://openalex.org/W2036355408","https://openalex.org/W2086775835","https://openalex.org/W2099220296","https://openalex.org/W2102333133","https://openalex.org/W2109906966","https://openalex.org/W2114067856","https://openalex.org/W2116548071","https://openalex.org/W2118866757","https://openalex.org/W2128765420","https://openalex.org/W2134807578","https://openalex.org/W2135431166","https://openalex.org/W2138406631","https://openalex.org/W2138843457","https://openalex.org/W2139802090","https://openalex.org/W2140210510","https://openalex.org/W2142682265","https://openalex.org/W2142891960","https://openalex.org/W2148051985","https://openalex.org/W2153185479","https://openalex.org/W2156348954","https://openalex.org/W2165158385","https://openalex.org/W2165350428","https://openalex.org/W3148529197","https://openalex.org/W4229487452","https://openalex.org/W4246219036","https://openalex.org/W4252742548","https://openalex.org/W4256338358"],"related_works":["https://openalex.org/W1942542608","https://openalex.org/W2353958330","https://openalex.org/W2049342712","https://openalex.org/W2103250493","https://openalex.org/W2137995472","https://openalex.org/W4242411138","https://openalex.org/W2581286023","https://openalex.org/W2054117411","https://openalex.org/W2357256492","https://openalex.org/W3022819336"],"abstract_inverted_index":{"Designing":[0],"energy-efficient":[1],"Digital":[2],"Signal":[3],"Processor":[4],"(DSP)":[5],"cores":[6],"has":[7],"become":[8],"a":[9,51],"key":[10],"concern":[11],"in":[12],"embedded":[13],"systems":[14],"development.":[15],"This":[16],"paper":[17],"proposes":[18],"an":[19,60],"energy-proportional":[20],"computing":[21],"scheme":[22],"for":[23,91],"Very":[24],"Long":[25],"Instruction":[26],"Word":[27],"(VLIW)":[28],"architectures.":[29],"To":[30],"make":[31],"the":[32,65,74,102,109],"processor":[33],"power":[34,111],"scales":[35],"with":[36],"adapted":[37],"parallelism,":[38],"we":[39,57],"propose":[40,59],"incorporating":[41],"distributed":[42],"Power-Gated":[43],"Register":[44],"Files":[45],"(PGRF)":[46],"into":[47],"VLIW":[48],"to":[49,78],"achieve":[50],"PGRF-VLIW":[52],"architecture.":[53],"For":[54],"energy":[55,82],"efficiency,":[56],"also":[58],"instruction":[61],"scheduling":[62],"algorithm":[63,72],"called":[64],"Deadline-Constrained":[66],"Clustered":[67],"Scheduling":[68],"(DCCS)":[69],"algorithm.":[70],"The":[71,96],"clusters":[73],"data":[75,80,93],"dependence":[76,94],"graph":[77],"reduce":[79],"transfer":[81],"and":[83,104,113],"makes":[84],"optimal":[85],"use":[86],"of":[87,98],"low-powered":[88],"local":[89],"registers":[90],"tree-structured":[92],"graphs.":[95],"results":[97],"evaluations":[99],"conducted":[100],"using":[101],"MiBench":[103],"DSPstone":[105],"benchmark":[106],"suites":[107],"substantiate":[108],"expected":[110],"saving":[112],"scaling":[114],"effects.":[115]},"counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2016,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}