{"id":"https://openalex.org/W2133867543","doi":"https://doi.org/10.1145/2627369.2627665","title":"Gated low-power clock tree synthesis for 3D-ICs","display_name":"Gated low-power clock tree synthesis for 3D-ICs","publication_year":2014,"publication_date":"2014-08-01","ids":{"openalex":"https://openalex.org/W2133867543","doi":"https://doi.org/10.1145/2627369.2627665","mag":"2133867543"},"language":"en","primary_location":{"id":"doi:10.1145/2627369.2627665","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2627369.2627665","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2014 international symposium on Low power electronics and design","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5064115741","display_name":"Tiantao Lu","orcid":"https://orcid.org/0000-0003-4431-811X"},"institutions":[{"id":"https://openalex.org/I66946132","display_name":"University of Maryland, College Park","ror":"https://ror.org/047s2c258","country_code":"US","type":"education","lineage":["https://openalex.org/I66946132"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Tiantao Lu","raw_affiliation_strings":["University of Maryland, Collge Park, MD, USA","Department of Electrical & Computer Engineering, University of Maryland, College Park, U.S.A"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Maryland, Collge Park, MD, USA","institution_ids":["https://openalex.org/I66946132"]},{"raw_affiliation_string":"Department of Electrical & Computer Engineering, University of Maryland, College Park, U.S.A","institution_ids":["https://openalex.org/I66946132"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5089770783","display_name":"Ankur Srivastava","orcid":"https://orcid.org/0000-0002-5445-904X"},"institutions":[{"id":"https://openalex.org/I66946132","display_name":"University of Maryland, College Park","ror":"https://ror.org/047s2c258","country_code":"US","type":"education","lineage":["https://openalex.org/I66946132"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ankur Srivastava","raw_affiliation_strings":["University of Maryland, Collge Park, MD, USA","Department of Electrical & Computer Engineering, University of Maryland, College Park, U.S.A"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Maryland, Collge Park, MD, USA","institution_ids":["https://openalex.org/I66946132"]},{"raw_affiliation_string":"Department of Electrical & Computer Engineering, University of Maryland, College Park, U.S.A","institution_ids":["https://openalex.org/I66946132"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I66946132"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"319","last_page":"322"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.6991509199142456},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.654984176158905},{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.6282572746276855},{"id":"https://openalex.org/keywords/timing-failure","display_name":"Timing failure","score":0.6152133941650391},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.562696099281311},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5311887264251709},{"id":"https://openalex.org/keywords/shutdown","display_name":"Shutdown","score":0.5059985518455505},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.5015072822570801},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.49915194511413574},{"id":"https://openalex.org/keywords/simulated-annealing","display_name":"Simulated annealing","score":0.4569121301174164},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.452747642993927},{"id":"https://openalex.org/keywords/clock-network","display_name":"Clock network","score":0.44787389039993286},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4187268614768982},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3669915199279785},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.32802683115005493},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.23987671732902527},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.19390976428985596},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.18335333466529846},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.17900198698043823}],"concepts":[{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.6991509199142456},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.654984176158905},{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.6282572746276855},{"id":"https://openalex.org/C104654189","wikidata":"https://www.wikidata.org/wiki/Q7806740","display_name":"Timing failure","level":5,"score":0.6152133941650391},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.562696099281311},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5311887264251709},{"id":"https://openalex.org/C2780263472","wikidata":"https://www.wikidata.org/wiki/Q331902","display_name":"Shutdown","level":2,"score":0.5059985518455505},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.5015072822570801},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.49915194511413574},{"id":"https://openalex.org/C126980161","wikidata":"https://www.wikidata.org/wiki/Q863783","display_name":"Simulated annealing","level":2,"score":0.4569121301174164},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.452747642993927},{"id":"https://openalex.org/C2778182565","wikidata":"https://www.wikidata.org/wiki/Q1752879","display_name":"Clock network","level":5,"score":0.44787389039993286},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4187268614768982},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3669915199279785},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.32802683115005493},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.23987671732902527},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.19390976428985596},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.18335333466529846},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.17900198698043823},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C116915560","wikidata":"https://www.wikidata.org/wiki/Q83504","display_name":"Nuclear engineering","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2627369.2627665","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2627369.2627665","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2014 international symposium on Low power electronics and design","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.7200000286102295}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1978169009","https://openalex.org/W2035957933","https://openalex.org/W2123953188","https://openalex.org/W2124955733","https://openalex.org/W2127128585","https://openalex.org/W2128876681","https://openalex.org/W2133279383","https://openalex.org/W2136047350","https://openalex.org/W2136529615","https://openalex.org/W2136768070","https://openalex.org/W2143629014","https://openalex.org/W2149996407","https://openalex.org/W2158473722","https://openalex.org/W2163961680"],"related_works":["https://openalex.org/W2088914741","https://openalex.org/W4247180033","https://openalex.org/W2559451387","https://openalex.org/W2144282137","https://openalex.org/W2617666058","https://openalex.org/W2127892766","https://openalex.org/W2803012234","https://openalex.org/W2199871724","https://openalex.org/W1490763633","https://openalex.org/W2165139624"],"abstract_inverted_index":{"In":[0,18],"this":[1],"paper,":[2],"we":[3,26,56],"minimize":[4],"3D":[5],"clock":[6,16,65,84,99],"power":[7,59,85],"using":[8],"shutdown":[9,20,44,73],"gates":[10,45],"to":[11,39],"selectively":[12],"turn":[13],"off":[14],"unnecessary":[15],"activities.":[17],"3D-IC,":[19],"signals":[21],"require":[22],"large-sized":[23],"Through-Silicon-Vias(TSVs),":[24],"so":[25],"propose":[27],"a":[28,35],"simulated":[29],"annealing(SA)":[30],"based":[31],"algorithm":[32],"along":[33],"with":[34,71,90],"force-directed":[36],"TSV":[37],"placer":[38],"decide":[40],"the":[41,47,64,72,82],"selection":[42],"of":[43,49],"and":[46],"locations":[48],"TSVs":[50],"under":[51],"layout":[52],"whitespace":[53],"constraint.":[54],"Furthermore,":[55],"recognize":[57],"optimal":[58],"saving":[60],"is":[61,68],"achieved":[62],"when":[63],"tree":[66],"itself":[67],"designed":[69],"simultaneously":[70],"network.":[74],"Experimental":[75],"results":[76],"show":[77],"that":[78],"our":[79],"heuristic":[80],"decreases":[81],"total":[83],"by":[86],"more":[87],"than":[88,92],"20%":[89],"less":[91],"1.5%":[93],"wirelength":[94],"overhead":[95],"while":[96],"ensuring":[97],"zero":[98],"skew.":[100]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":2}],"updated_date":"2026-07-15T18:14:33.161393","created_date":"2025-10-10T00:00:00"}