{"id":"https://openalex.org/W2027639183","doi":"https://doi.org/10.1145/2609248.2609256","title":"A framework for dynamic parallelization of FPGA-accelerated applications","display_name":"A framework for dynamic parallelization of FPGA-accelerated applications","publication_year":2014,"publication_date":"2014-05-30","ids":{"openalex":"https://openalex.org/W2027639183","doi":"https://doi.org/10.1145/2609248.2609256","mag":"2027639183"},"language":"en","primary_location":{"id":"doi:10.1145/2609248.2609256","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2609248.2609256","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 17th International Workshop on Software and Compilers for Embedded Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5016246137","display_name":"Jeremy Fowers","orcid":null},"institutions":[{"id":"https://openalex.org/I33213144","display_name":"University of Florida","ror":"https://ror.org/02y3ad647","country_code":"US","type":"education","lineage":["https://openalex.org/I33213144"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Jeremy Fowers","raw_affiliation_strings":["University of Florida, Gainesville, FL"],"affiliations":[{"raw_affiliation_string":"University of Florida, Gainesville, FL","institution_ids":["https://openalex.org/I33213144"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108092986","display_name":"Jianye Liu","orcid":null},"institutions":[{"id":"https://openalex.org/I33213144","display_name":"University of Florida","ror":"https://ror.org/02y3ad647","country_code":"US","type":"education","lineage":["https://openalex.org/I33213144"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jianye Liu","raw_affiliation_strings":["University of Florida, Gainesville, FL"],"affiliations":[{"raw_affiliation_string":"University of Florida, Gainesville, FL","institution_ids":["https://openalex.org/I33213144"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5088031457","display_name":"Greg Stitt","orcid":"https://orcid.org/0000-0001-7159-7439"},"institutions":[{"id":"https://openalex.org/I33213144","display_name":"University of Florida","ror":"https://ror.org/02y3ad647","country_code":"US","type":"education","lineage":["https://openalex.org/I33213144"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Greg Stitt","raw_affiliation_strings":["University of Florida, Gainesville, FL"],"affiliations":[{"raw_affiliation_string":"University of Florida, Gainesville, FL","institution_ids":["https://openalex.org/I33213144"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5016246137"],"corresponding_institution_ids":["https://openalex.org/I33213144"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.09331205,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"10"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8997719287872314},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.8318560123443604},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.7899882793426514},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.7504557371139526},{"id":"https://openalex.org/keywords/compile-time","display_name":"Compile time","score":0.6458841562271118},{"id":"https://openalex.org/keywords/exploit","display_name":"Exploit","score":0.6007205247879028},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5409349799156189},{"id":"https://openalex.org/keywords/optimizing-compiler","display_name":"Optimizing compiler","score":0.5066671967506409},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.49620991945266724},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.42821285128593445},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.24736422300338745},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.19954127073287964}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8997719287872314},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.8318560123443604},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.7899882793426514},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.7504557371139526},{"id":"https://openalex.org/C200833197","wikidata":"https://www.wikidata.org/wiki/Q333707","display_name":"Compile time","level":3,"score":0.6458841562271118},{"id":"https://openalex.org/C165696696","wikidata":"https://www.wikidata.org/wiki/Q11287","display_name":"Exploit","level":2,"score":0.6007205247879028},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5409349799156189},{"id":"https://openalex.org/C190902152","wikidata":"https://www.wikidata.org/wiki/Q1325106","display_name":"Optimizing compiler","level":3,"score":0.5066671967506409},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.49620991945266724},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.42821285128593445},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.24736422300338745},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.19954127073287964},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2609248.2609256","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2609248.2609256","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 17th International Workshop on Software and Compilers for Embedded Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G2628282949","display_name":null,"funder_award_id":"CNS-0914474, CNS-1149285","funder_id":"https://openalex.org/F4320337388","funder_display_name":"Division of Computer and Network Systems"}],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"},{"id":"https://openalex.org/F4320337388","display_name":"Division of Computer and Network Systems","ror":"https://ror.org/02rdzmk74"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":29,"referenced_works":["https://openalex.org/W165650166","https://openalex.org/W1509875415","https://openalex.org/W1523813310","https://openalex.org/W1949412827","https://openalex.org/W1964345099","https://openalex.org/W1969168818","https://openalex.org/W1971704691","https://openalex.org/W1977001153","https://openalex.org/W1994993486","https://openalex.org/W1996146601","https://openalex.org/W2018055497","https://openalex.org/W2028437460","https://openalex.org/W2034248530","https://openalex.org/W2052934867","https://openalex.org/W2071470850","https://openalex.org/W2074398758","https://openalex.org/W2090301322","https://openalex.org/W2097699872","https://openalex.org/W2106472852","https://openalex.org/W2112610639","https://openalex.org/W2114006602","https://openalex.org/W2127699991","https://openalex.org/W2134441275","https://openalex.org/W2140321074","https://openalex.org/W2142677441","https://openalex.org/W2152016786","https://openalex.org/W2161828193","https://openalex.org/W2253535924","https://openalex.org/W3083047093"],"related_works":["https://openalex.org/W2371266106","https://openalex.org/W2117382851","https://openalex.org/W1966837078","https://openalex.org/W3006505070","https://openalex.org/W2382449560","https://openalex.org/W2767298477","https://openalex.org/W2110432562","https://openalex.org/W2002505081","https://openalex.org/W2083681681","https://openalex.org/W2778498407"],"abstract_inverted_index":{"High-level":[0],"synthesis":[1],"and":[2,66],"compiler":[3],"studies":[4],"have":[5],"introduced":[6],"many":[7,36,48],"compile-time":[8,18],"techniques":[9],"for":[10,23,47,99],"parallelizing":[11],"applications.":[12],"However,":[13],"one":[14],"fundamental":[15],"limitation":[16],"of":[17,89,97,110,121],"optimization":[19],"is":[20,44],"the":[21,77],"requirement":[22],"pessimistic":[24],"dependence":[25],"assumptions":[26],"that":[27,43,56],"can":[28],"significantly":[29],"restrict":[30],"parallelism.":[31],"To":[32],"avoid":[33],"this":[34],"limitation,":[35],"compilers":[37],"require":[38],"a":[39,52,95,100,108,118],"restrictive":[40],"coding":[41],"style":[42],"not":[45],"practical":[46],"designers.":[49],"We":[50],"present":[51],"more":[53],"transparent":[54],"approach":[55,78],"aggressively":[57],"parallelizes":[58],"applications":[59],"by":[60],"dynamically":[61],"analyzing":[62],"actual":[63],"runtime":[64],"dependencies":[65,73],"scheduling":[67],"functions":[68],"onto":[69],"multiple":[70],"devices":[71],"when":[72],"allow.":[74],"In":[75],"addition,":[76],"applies":[79],"FPGA-specific":[80],"pipelining":[81],"optimizations":[82],"to":[83,104,113],"exploit":[84],"deep":[85],"parallelism":[86],"in":[87],"chains":[88],"dependent":[90],"functions.":[91],"Experimental":[92],"results":[93],"show":[94],"speedup":[96,109],"4.9x":[98],"video-processing":[101],"application":[102],"compared":[103,112],"sequential":[105],"software":[106],"execution,":[107,116],"5.6x":[111],"traditional":[114],"FPGA":[115],"with":[117],"framework":[119],"overhead":[120],"only":[122],"4%.":[123]},"counts_by_year":[{"year":2018,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}