{"id":"https://openalex.org/W2126830109","doi":"https://doi.org/10.1145/2597652.2597685","title":"Unified on-chip memory allocation for SIMT architecture","display_name":"Unified on-chip memory allocation for SIMT architecture","publication_year":2014,"publication_date":"2014-06-10","ids":{"openalex":"https://openalex.org/W2126830109","doi":"https://doi.org/10.1145/2597652.2597685","mag":"2126830109"},"language":"en","primary_location":{"id":"doi:10.1145/2597652.2597685","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2597652.2597685","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 28th ACM international conference on Supercomputing","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5070117880","display_name":"Ari B. Hayes","orcid":null},"institutions":[{"id":"https://openalex.org/I102322142","display_name":"Rutgers, The State University of New Jersey","ror":"https://ror.org/05vt9qd57","country_code":"US","type":"education","lineage":["https://openalex.org/I102322142"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ari B. Hayes","raw_affiliation_strings":["Rutgers University, Piscataway, NJ, USA","Rutgers University , Piscataway, NJ , USA ,"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Rutgers University, Piscataway, NJ, USA","institution_ids":["https://openalex.org/I102322142"]},{"raw_affiliation_string":"Rutgers University , Piscataway, NJ , USA ,","institution_ids":["https://openalex.org/I102322142"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5071204460","display_name":"Eddy Z. Zhang","orcid":"https://orcid.org/0000-0002-3815-4318"},"institutions":[{"id":"https://openalex.org/I102322142","display_name":"Rutgers, The State University of New Jersey","ror":"https://ror.org/05vt9qd57","country_code":"US","type":"education","lineage":["https://openalex.org/I102322142"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Eddy Z. Zhang","raw_affiliation_strings":["Rutgers University, Piscataway, NJ, USA","Rutgers University , Piscataway, NJ , USA ,"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Rutgers University, Piscataway, NJ, USA","institution_ids":["https://openalex.org/I102322142"]},{"raw_affiliation_string":"Rutgers University , Piscataway, NJ , USA ,","institution_ids":["https://openalex.org/I102322142"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I102322142"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":27,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"293","last_page":"302"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8640552759170532},{"id":"https://openalex.org/keywords/thread","display_name":"Thread (computing)","score":0.8136361241340637},{"id":"https://openalex.org/keywords/register-file","display_name":"Register file","score":0.6883172392845154},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6628668308258057},{"id":"https://openalex.org/keywords/context-switch","display_name":"Context switch","score":0.6578284502029419},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.5652896165847778},{"id":"https://openalex.org/keywords/concurrency","display_name":"Concurrency","score":0.5513925552368164},{"id":"https://openalex.org/keywords/processor-register","display_name":"Processor register","score":0.5012116432189941},{"id":"https://openalex.org/keywords/register-allocation","display_name":"Register allocation","score":0.48286062479019165},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.43887537717819214},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.3779699504375458},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.33292073011398315},{"id":"https://openalex.org/keywords/memory-address","display_name":"Memory address","score":0.1264277994632721},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.07785823941230774}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8640552759170532},{"id":"https://openalex.org/C138101251","wikidata":"https://www.wikidata.org/wiki/Q213092","display_name":"Thread (computing)","level":2,"score":0.8136361241340637},{"id":"https://openalex.org/C117280010","wikidata":"https://www.wikidata.org/wiki/Q180944","display_name":"Register file","level":3,"score":0.6883172392845154},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6628668308258057},{"id":"https://openalex.org/C53833338","wikidata":"https://www.wikidata.org/wiki/Q1061424","display_name":"Context switch","level":2,"score":0.6578284502029419},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5652896165847778},{"id":"https://openalex.org/C193702766","wikidata":"https://www.wikidata.org/wiki/Q1414548","display_name":"Concurrency","level":2,"score":0.5513925552368164},{"id":"https://openalex.org/C2871975","wikidata":"https://www.wikidata.org/wiki/Q187466","display_name":"Processor register","level":4,"score":0.5012116432189941},{"id":"https://openalex.org/C128916667","wikidata":"https://www.wikidata.org/wiki/Q1343660","display_name":"Register allocation","level":3,"score":0.48286062479019165},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.43887537717819214},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.3779699504375458},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.33292073011398315},{"id":"https://openalex.org/C153247305","wikidata":"https://www.wikidata.org/wiki/Q835713","display_name":"Memory address","level":3,"score":0.1264277994632721},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.07785823941230774},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2597652.2597685","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2597652.2597685","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 28th ACM international conference on Supercomputing","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320309480","display_name":"Nvidia","ror":"https://ror.org/03jdj4y14"},{"id":"https://openalex.org/F4320333987","display_name":"Research Council, Rutgers, The State University of New Jersey","ror":null}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":29,"referenced_works":["https://openalex.org/W1564196930","https://openalex.org/W1870686413","https://openalex.org/W1883303451","https://openalex.org/W1980364632","https://openalex.org/W2003804316","https://openalex.org/W2010867025","https://openalex.org/W2013419729","https://openalex.org/W2018150881","https://openalex.org/W2069329354","https://openalex.org/W2080592089","https://openalex.org/W2084110734","https://openalex.org/W2097701997","https://openalex.org/W2106579652","https://openalex.org/W2110549003","https://openalex.org/W2118866757","https://openalex.org/W2120062497","https://openalex.org/W2130749431","https://openalex.org/W2140191557","https://openalex.org/W2142769604","https://openalex.org/W2145456033","https://openalex.org/W2154213129","https://openalex.org/W2155548817","https://openalex.org/W2160313335","https://openalex.org/W2162528816","https://openalex.org/W2167822297","https://openalex.org/W2172062522","https://openalex.org/W3022528408","https://openalex.org/W3148529197","https://openalex.org/W4232640234"],"related_works":["https://openalex.org/W1967889241","https://openalex.org/W2111377238","https://openalex.org/W2161297616","https://openalex.org/W3117494601","https://openalex.org/W4247209662","https://openalex.org/W2195435904","https://openalex.org/W2148662141","https://openalex.org/W2159389028","https://openalex.org/W2224192221","https://openalex.org/W2884590322"],"abstract_inverted_index":{"The":[0,58],"popularity":[1],"of":[2,32,36,78,110],"general":[3],"purpose":[4],"Graphic":[5],"Processing":[6],"Unit":[7],"(GPU)":[8],"is":[9,48],"largely":[10],"attributed":[11],"to":[12,40,51,101,106,116],"the":[13,30,46,76,84,95,102,107,126],"tremendous":[14],"concurrency":[15],"enabled":[16],"by":[17],"its":[18],"underlying":[19],"architecture":[20,60],"--":[21],"single":[22,122],"instruction":[23],"multiple":[24],"thread":[25,123],"(SIMT)":[26],"architecture.":[27],"It":[28],"keeps":[29],"context":[31],"a":[33,62],"significant":[34],"number":[35,77],"threads":[37],"in":[38,94],"registers":[39],"enable":[41],"fast":[42],"``context":[43],"switches\"":[44],"when":[45],"processor":[47],"stalled":[49],"due":[50,105],"execution":[52,109],"dependence,":[53],"memory":[54],"requests":[55],"and":[56],"etc.":[57],"SIMT":[59],"has":[61],"large":[63],"register":[64,73,89,103],"file":[65],"evenly":[66],"partitioned":[67],"among":[68],"all":[69],"concurrent":[70,79,108],"threads.":[71,112],"Per-thread":[72],"usage":[74],"determines":[75],"threads,":[80],"which":[81],"strongly":[82],"affects":[83],"whole":[85,127],"program":[86],"performance.":[87,129],"Existing":[88],"allocation":[90],"techniques,":[91],"extensively":[92],"studied":[93],"past":[96],"several":[97],"decades,":[98],"are":[99,114],"oblivious":[100],"contention":[104],"many":[111],"They":[113],"prone":[115],"making":[117],"optimization":[118],"decisions":[119],"that":[120],"benefit":[121],"but":[124],"degrade":[125],"application":[128]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":5},{"year":2018,"cited_by_count":4},{"year":2017,"cited_by_count":5},{"year":2016,"cited_by_count":6},{"year":2015,"cited_by_count":3}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}