{"id":"https://openalex.org/W2121090357","doi":"https://doi.org/10.1145/2597652.2597654","title":"Collective memory transfers for multi-core chips","display_name":"Collective memory transfers for multi-core chips","publication_year":2014,"publication_date":"2014-06-10","ids":{"openalex":"https://openalex.org/W2121090357","doi":"https://doi.org/10.1145/2597652.2597654","mag":"2121090357"},"language":"en","primary_location":{"id":"doi:10.1145/2597652.2597654","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2597652.2597654","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 28th ACM international conference on Supercomputing","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://escholarship.org/uc/item/36t430gk","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5038069067","display_name":"George Michelogiannakis","orcid":"https://orcid.org/0000-0003-3743-6054"},"institutions":[{"id":"https://openalex.org/I148283060","display_name":"Lawrence Berkeley National Laboratory","ror":"https://ror.org/02jbv0t02","country_code":"US","type":"facility","lineage":["https://openalex.org/I1330989302","https://openalex.org/I148283060","https://openalex.org/I39565521"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"George Michelogiannakis","raw_affiliation_strings":["Lawrence Berkeley National Laboratory, Berkeley, CA, USA","Lawrence Berkeley National Laboratory, Berkeley, CA USA#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Lawrence Berkeley National Laboratory, Berkeley, CA, USA","institution_ids":["https://openalex.org/I148283060"]},{"raw_affiliation_string":"Lawrence Berkeley National Laboratory, Berkeley, CA USA#TAB#","institution_ids":["https://openalex.org/I148283060"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101624343","display_name":"Alexander Williams","orcid":"https://orcid.org/0000-0003-2487-6667"},"institutions":[{"id":"https://openalex.org/I148283060","display_name":"Lawrence Berkeley National Laboratory","ror":"https://ror.org/02jbv0t02","country_code":"US","type":"facility","lineage":["https://openalex.org/I1330989302","https://openalex.org/I148283060","https://openalex.org/I39565521"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Alexander Williams","raw_affiliation_strings":["Lawrence Berkeley National Laboratory, Berkeley, CA, USA","Lawrence Berkeley National Laboratory, Berkeley, CA USA#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Lawrence Berkeley National Laboratory, Berkeley, CA, USA","institution_ids":["https://openalex.org/I148283060"]},{"raw_affiliation_string":"Lawrence Berkeley National Laboratory, Berkeley, CA USA#TAB#","institution_ids":["https://openalex.org/I148283060"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102746800","display_name":"Samuel Williams","orcid":"https://orcid.org/0000-0002-8327-5717"},"institutions":[{"id":"https://openalex.org/I148283060","display_name":"Lawrence Berkeley National Laboratory","ror":"https://ror.org/02jbv0t02","country_code":"US","type":"facility","lineage":["https://openalex.org/I1330989302","https://openalex.org/I148283060","https://openalex.org/I39565521"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Samuel Williams","raw_affiliation_strings":["Lawrence Berkeley National Laboratory, Berkeley, CA, USA","Lawrence Berkeley National Laboratory, Berkeley, CA USA#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Lawrence Berkeley National Laboratory, Berkeley, CA, USA","institution_ids":["https://openalex.org/I148283060"]},{"raw_affiliation_string":"Lawrence Berkeley National Laboratory, Berkeley, CA USA#TAB#","institution_ids":["https://openalex.org/I148283060"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5010873686","display_name":"John Shalf","orcid":"https://orcid.org/0000-0002-0608-3690"},"institutions":[{"id":"https://openalex.org/I148283060","display_name":"Lawrence Berkeley National Laboratory","ror":"https://ror.org/02jbv0t02","country_code":"US","type":"facility","lineage":["https://openalex.org/I1330989302","https://openalex.org/I148283060","https://openalex.org/I39565521"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"John Shalf","raw_affiliation_strings":["Lawrence Berkeley National Laboratory, Berkeley, CA, USA","Lawrence Berkeley National Laboratory, Berkeley, CA USA#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Lawrence Berkeley National Laboratory, Berkeley, CA, USA","institution_ids":["https://openalex.org/I148283060"]},{"raw_affiliation_string":"Lawrence Berkeley National Laboratory, Berkeley, CA USA#TAB#","institution_ids":["https://openalex.org/I148283060"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I148283060"],"apc_list":null,"apc_paid":null,"fwci":0.6046,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.63045099,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"343","last_page":"352"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8033734560012817},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.662881076335907},{"id":"https://openalex.org/keywords/cas-latency","display_name":"CAS latency","score":0.6070932149887085},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.5698572993278503},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5515393018722534},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.4564807713031769},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.44769537448883057},{"id":"https://openalex.org/keywords/registered-memory","display_name":"Registered memory","score":0.4442494809627533},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4385390877723694},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.43685147166252136},{"id":"https://openalex.org/keywords/memory-architecture","display_name":"Memory architecture","score":0.4255378544330597},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4212072491645813},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3864884376525879},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.3266575336456299},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.32544374465942383}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8033734560012817},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.662881076335907},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.6070932149887085},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.5698572993278503},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5515393018722534},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.4564807713031769},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.44769537448883057},{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.4442494809627533},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4385390877723694},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.43685147166252136},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.4255378544330597},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4212072491645813},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3864884376525879},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.3266575336456299},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.32544374465942383},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":6,"locations":[{"id":"doi:10.1145/2597652.2597654","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2597652.2597654","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 28th ACM international conference on Supercomputing","raw_type":"proceedings-article"},{"id":"pmh:ark:/13030/qt36t430gk","is_oa":false,"landing_page_url":null,"pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":null},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.429.3285","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.429.3285","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://people.csail.mit.edu/skamil/wosc/papers/mihelog.pdf","raw_type":"text"},{"id":"pmh:oai:escholarship.org/ark:/13030/qt1bd1b00p","is_oa":false,"landing_page_url":"https://escholarship.org/uc/item/1bd1b00p","pdf_url":null,"source":{"id":"https://openalex.org/S4306400115","display_name":"eScholarship (California Digital Library)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I2801248553","host_organization_name":"California Digital Library","host_organization_lineage":["https://openalex.org/I2801248553"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"article"},{"id":"pmh:oai:escholarship.org:ark:/13030/qt36t430gk","is_oa":true,"landing_page_url":"https://escholarship.org/uc/item/36t430gk","pdf_url":null,"source":{"id":"https://openalex.org/S4306400115","display_name":"eScholarship (California Digital Library)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I2801248553","host_organization_name":"California Digital Library","host_organization_lineage":["https://openalex.org/I2801248553"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"article"},{"id":"pmh:qt1bd1b00p","is_oa":false,"landing_page_url":"http://www.escholarship.org/uc/item/1bd1b00p","pdf_url":null,"source":{"id":"https://openalex.org/S4306400115","display_name":"eScholarship (California Digital Library)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I2801248553","host_organization_name":"California Digital Library","host_organization_lineage":["https://openalex.org/I2801248553"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Michelogiannakis, George. (2014). Collective Memory Transfers for Multi-Core Chips. Lawrence Berkeley National Laboratory: Lawrence Berkeley National Laboratory. Retrieved from: http://www.escholarship.org/uc/item/1bd1b00p","raw_type":"article"}],"best_oa_location":{"id":"pmh:oai:escholarship.org:ark:/13030/qt36t430gk","is_oa":true,"landing_page_url":"https://escholarship.org/uc/item/36t430gk","pdf_url":null,"source":{"id":"https://openalex.org/S4306400115","display_name":"eScholarship (California Digital Library)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I2801248553","host_organization_name":"California Digital Library","host_organization_lineage":["https://openalex.org/I2801248553"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"article"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":91,"referenced_works":["https://openalex.org/W35708471","https://openalex.org/W128386270","https://openalex.org/W292088311","https://openalex.org/W1485904170","https://openalex.org/W1488639170","https://openalex.org/W1501077214","https://openalex.org/W1503198237","https://openalex.org/W1519701134","https://openalex.org/W1544567909","https://openalex.org/W1559264847","https://openalex.org/W1837653564","https://openalex.org/W1926601941","https://openalex.org/W1974211070","https://openalex.org/W1981812667","https://openalex.org/W1987588924","https://openalex.org/W1987749257","https://openalex.org/W1993488239","https://openalex.org/W1994249978","https://openalex.org/W1997576530","https://openalex.org/W2002907208","https://openalex.org/W2006312753","https://openalex.org/W2007448134","https://openalex.org/W2007929622","https://openalex.org/W2016618963","https://openalex.org/W2020636597","https://openalex.org/W2025971662","https://openalex.org/W2026517532","https://openalex.org/W2029046561","https://openalex.org/W2031866163","https://openalex.org/W2034761517","https://openalex.org/W2035430533","https://openalex.org/W2035720033","https://openalex.org/W2038509324","https://openalex.org/W2040073568","https://openalex.org/W2064344201","https://openalex.org/W2071522743","https://openalex.org/W2079498535","https://openalex.org/W2081286217","https://openalex.org/W2087479145","https://openalex.org/W2088032806","https://openalex.org/W2088260668","https://openalex.org/W2090683636","https://openalex.org/W2091434413","https://openalex.org/W2091545779","https://openalex.org/W2096085985","https://openalex.org/W2096968694","https://openalex.org/W2097876246","https://openalex.org/W2102081731","https://openalex.org/W2105332698","https://openalex.org/W2107333973","https://openalex.org/W2111667319","https://openalex.org/W2113253469","https://openalex.org/W2115172404","https://openalex.org/W2115220969","https://openalex.org/W2118231264","https://openalex.org/W2118703320","https://openalex.org/W2124931755","https://openalex.org/W2127454998","https://openalex.org/W2134573462","https://openalex.org/W2135682468","https://openalex.org/W2137613189","https://openalex.org/W2138661001","https://openalex.org/W2140305245","https://openalex.org/W2141435354","https://openalex.org/W2142972517","https://openalex.org/W2144154231","https://openalex.org/W2144481293","https://openalex.org/W2145871983","https://openalex.org/W2151811992","https://openalex.org/W2151917022","https://openalex.org/W2154078685","https://openalex.org/W2154786353","https://openalex.org/W2155371841","https://openalex.org/W2157152271","https://openalex.org/W2158620667","https://openalex.org/W2159908132","https://openalex.org/W2160220170","https://openalex.org/W2160875256","https://openalex.org/W2160915649","https://openalex.org/W2162639668","https://openalex.org/W2162838417","https://openalex.org/W2168014483","https://openalex.org/W2170886848","https://openalex.org/W2237817213","https://openalex.org/W2542068122","https://openalex.org/W2601699856","https://openalex.org/W3152199537","https://openalex.org/W3152438252","https://openalex.org/W4236382111","https://openalex.org/W4247787189","https://openalex.org/W6638708518"],"related_works":["https://openalex.org/W3008068282","https://openalex.org/W2185658074","https://openalex.org/W2896161911","https://openalex.org/W4285245242","https://openalex.org/W2907559171","https://openalex.org/W2019238062","https://openalex.org/W2138825797","https://openalex.org/W4243618206","https://openalex.org/W4393076761","https://openalex.org/W2155643858"],"abstract_inverted_index":{"Future":[0],"performance":[1,49],"improvements":[2,17],"for":[3,18,41],"microprocessors":[4],"have":[5],"shifted":[6],"from":[7,31,110],"clock":[8],"frequency":[9],"scaling":[10],"towards":[11],"increases":[12],"in":[13,35,88],"on-chip":[14,42,112],"parallelism.":[15],"Performance":[16],"a":[19,32,38,132],"wide":[20],"variety":[21],"of":[22,28,100],"parallel":[23],"applications":[24],"require":[25],"domain":[26],"decomposition":[27],"data":[29,107,142],"arrays":[30],"contiguous":[33],"arrangement":[34],"memory":[36,67,89,94,116],"to":[37,77,92,108,115,126,131],"tiled":[39],"layout":[40],"L1":[43],"caches":[44],"and":[45,74,81,85,103,139,152],"scratchpads.":[46],"However,":[47],"DRAM":[48,147],"suffers":[50],"under":[51],"the":[52,93,111],"non-streaming":[53],"access":[54],"patterns":[55],"generated":[56],"by":[57,124,150,155],"many":[58],"independent":[59],"cores.":[60],"In":[61],"this":[62],"paper,":[63],"we":[64],"propose":[65],"collective":[66,79,101],"scheduling":[68],"(CMS)":[69],"that":[70,83],"uses":[71],"simple":[72],"software":[73],"inexpensive":[75],"hardware":[76],"identify":[78],"transfers":[80,102],"guarantee":[82],"loads":[84],"stores":[86],"arrive":[87],"address":[90,117],"order":[91],"controller.":[95],"CMS":[96,119,144],"actively":[97],"takes":[98],"charge":[99],"pushes":[104],"or":[105,109],"pulls":[106],"processors":[113],"according":[114],"order.":[118],"reduces":[120,146],"application":[121],"execution":[122],"time":[123],"up":[125],"55%":[127],"(20%":[128],"average)":[129],"compared":[130],"state-of-the-art":[133],"architecture":[134],"where":[135],"each":[136],"processor":[137],"reads":[138],"writes":[140],"its":[141],"independently.":[143],"also":[145],"read":[148],"power":[149,154],"2.2\u00d7":[151],"write":[153],"50%.":[156]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2014,"cited_by_count":2}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}