{"id":"https://openalex.org/W2080414452","doi":"https://doi.org/10.1145/2591513.2591589","title":"A dual-rail LUT for reconfigurable logic using null convention logic","display_name":"A dual-rail LUT for reconfigurable logic using null convention logic","publication_year":2014,"publication_date":"2014-05-20","ids":{"openalex":"https://openalex.org/W2080414452","doi":"https://doi.org/10.1145/2591513.2591589","mag":"2080414452"},"language":"en","primary_location":{"id":"doi:10.1145/2591513.2591589","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2591513.2591589","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 24th edition of the great lakes symposium on VLSI","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://figshare.com/articles/conference_contribution/A_dual-rail_LUT_for_reconfigurable_logic_using_null_convention_logic/27390504","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5050521393","display_name":"Jing Xiao Yu","orcid":null},"institutions":[{"id":"https://openalex.org/I82951845","display_name":"RMIT University","ror":"https://ror.org/04ttjf776","country_code":"AU","type":"education","lineage":["https://openalex.org/I82951845"]}],"countries":["AU"],"is_corresponding":false,"raw_author_name":"Jing Yu","raw_affiliation_strings":["RMIT University, Melbourne, Australia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"RMIT University, Melbourne, Australia","institution_ids":["https://openalex.org/I82951845"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5103092491","display_name":"Paul Beckett","orcid":"https://orcid.org/0000-0001-8401-5477"},"institutions":[{"id":"https://openalex.org/I82951845","display_name":"RMIT University","ror":"https://ror.org/04ttjf776","country_code":"AU","type":"education","lineage":["https://openalex.org/I82951845"]}],"countries":["AU"],"is_corresponding":false,"raw_author_name":"Paul Beckett","raw_affiliation_strings":["RMIT University, Melbourne, Australia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"RMIT University, Melbourne, Australia","institution_ids":["https://openalex.org/I82951845"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I82951845"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.12376944,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"261","last_page":"266"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6719763278961182},{"id":"https://openalex.org/keywords/logic-block","display_name":"Logic block","score":0.6045302152633667},{"id":"https://openalex.org/keywords/asynchronous-circuit","display_name":"Asynchronous circuit","score":0.587369978427887},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.5679309964179993},{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.5619935989379883},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.5343140363693237},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5334266424179077},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.5129265785217285},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5129241943359375},{"id":"https://openalex.org/keywords/programmable-logic-array","display_name":"Programmable logic array","score":0.5088505744934082},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5080966949462891},{"id":"https://openalex.org/keywords/programmable-array-logic","display_name":"Programmable Array Logic","score":0.4924987256526947},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.49190354347229004},{"id":"https://openalex.org/keywords/synchronizing","display_name":"Synchronizing","score":0.4692395031452179},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4621238708496094},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.4361193776130676},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.4245876669883728},{"id":"https://openalex.org/keywords/register-transfer-level","display_name":"Register-transfer level","score":0.4188387393951416},{"id":"https://openalex.org/keywords/function-block-diagram","display_name":"Function block diagram","score":0.4166318476200104},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.416460782289505},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3985438346862793},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.2015024721622467},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.18829277157783508},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.15241166949272156},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.10001954436302185},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.07345622777938843},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.07202693819999695}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6719763278961182},{"id":"https://openalex.org/C2778325283","wikidata":"https://www.wikidata.org/wiki/Q1125244","display_name":"Logic block","level":3,"score":0.6045302152633667},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.587369978427887},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.5679309964179993},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.5619935989379883},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.5343140363693237},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5334266424179077},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.5129265785217285},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5129241943359375},{"id":"https://openalex.org/C182322920","wikidata":"https://www.wikidata.org/wiki/Q2112217","display_name":"Programmable logic array","level":3,"score":0.5088505744934082},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5080966949462891},{"id":"https://openalex.org/C113323844","wikidata":"https://www.wikidata.org/wiki/Q1378651","display_name":"Programmable Array Logic","level":5,"score":0.4924987256526947},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.49190354347229004},{"id":"https://openalex.org/C162932704","wikidata":"https://www.wikidata.org/wiki/Q1058791","display_name":"Synchronizing","level":3,"score":0.4692395031452179},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4621238708496094},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.4361193776130676},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.4245876669883728},{"id":"https://openalex.org/C34854456","wikidata":"https://www.wikidata.org/wiki/Q1484552","display_name":"Register-transfer level","level":4,"score":0.4188387393951416},{"id":"https://openalex.org/C61505648","wikidata":"https://www.wikidata.org/wiki/Q625752","display_name":"Function block diagram","level":3,"score":0.4166318476200104},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.416460782289505},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3985438346862793},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.2015024721622467},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.18829277157783508},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.15241166949272156},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.10001954436302185},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.07345622777938843},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.07202693819999695},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C761482","wikidata":"https://www.wikidata.org/wiki/Q118093","display_name":"Transmission (telecommunications)","level":2,"score":0.0},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.0},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1145/2591513.2591589","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2591513.2591589","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 24th edition of the great lakes symposium on VLSI","raw_type":"proceedings-article"},{"id":"pmh:oai:alma.61RMIT_INST:11247818910001341","is_oa":false,"landing_page_url":"http://doi.org/10.1145/2591513.2591589","pdf_url":null,"source":{"id":"https://openalex.org/S4306402074","display_name":"RMIT Research Repository (RMIT University Library)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I82951845","host_organization_name":"RMIT University","host_organization_lineage":["https://openalex.org/I82951845"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"text"},{"id":"pmh:oai:figshare.com:article/27390504","is_oa":true,"landing_page_url":"https://figshare.com/articles/conference_contribution/A_dual-rail_LUT_for_reconfigurable_logic_using_null_convention_logic/27390504","pdf_url":null,"source":{"id":"https://openalex.org/S4377196282","display_name":"Figshare","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4210132348","host_organization_name":"Figshare (United Kingdom)","host_organization_lineage":["https://openalex.org/I4210132348"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Conference contribution"}],"best_oa_location":{"id":"pmh:oai:figshare.com:article/27390504","is_oa":true,"landing_page_url":"https://figshare.com/articles/conference_contribution/A_dual-rail_LUT_for_reconfigurable_logic_using_null_convention_logic/27390504","pdf_url":null,"source":{"id":"https://openalex.org/S4377196282","display_name":"Figshare","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4210132348","host_organization_name":"Figshare (United Kingdom)","host_organization_lineage":["https://openalex.org/I4210132348"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Conference contribution"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W1527534371","https://openalex.org/W1549700718","https://openalex.org/W1561252668","https://openalex.org/W1853963567","https://openalex.org/W1966573088","https://openalex.org/W2036926171","https://openalex.org/W2098326421","https://openalex.org/W2116976796","https://openalex.org/W2117299791","https://openalex.org/W2120757256","https://openalex.org/W2145692097","https://openalex.org/W2162349600","https://openalex.org/W2163108907","https://openalex.org/W2567464592","https://openalex.org/W3042770083","https://openalex.org/W3197788851","https://openalex.org/W3210523556","https://openalex.org/W4231905827"],"related_works":["https://openalex.org/W2480852620","https://openalex.org/W2197466303","https://openalex.org/W2246445978","https://openalex.org/W2182398074","https://openalex.org/W3023652529","https://openalex.org/W2188536820","https://openalex.org/W2424214691","https://openalex.org/W3092973463","https://openalex.org/W2418552007","https://openalex.org/W2151927748"],"abstract_inverted_index":{"Both":[0,88],"asynchronous":[1,26,66],"and":[2,19,46,86,90,98,102],"reconfigurable":[3,65,69],"techniques":[4],"are":[5,52,60,93],"likely":[6],"to":[7,15,64,76],"become":[8],"increasingly":[9],"important":[10],"in":[11],"the":[12],"future":[13],"due":[14],"greater":[16],"device":[17],"unreliability":[18],"variability":[20],"at":[21],"nano-scale":[22],"dimensions.":[23],"One":[24],"promising":[25],"technique,":[27],"Null":[28],"Convention":[29],"Logic":[30],"(NCL)":[31],"is":[32,41,74,84,100],"a":[33,81],"symbolically":[34],"complete":[35],"quasi-delay":[36],"insensitive":[37],"logic":[38,58],"system":[39],"that":[40,73],"inherently":[42],"self-determined,":[43],"locally":[44],"autonomous":[45],"self-synchronizing.":[47],"As":[48],"current":[49],"FPGA":[50,82],"devices":[51],"set":[53],"up":[54],"for":[55],"clocked":[56],"synchronous":[57],"they":[59],"not":[61],"well":[62],"suited":[63],"systems.":[67],"A":[68],"block":[70,96],"supporting":[71],"NCL":[72],"intended":[75],"form":[77],"one":[78],"component":[79],"of":[80],"organization":[83],"proposed":[85],"analyzed.":[87],"single-rail":[89],"dual-rail":[91],"LUTs":[92],"described.":[94],"The":[95],"design":[97],"layout":[99],"described":[101],"analyzed":[103],"using":[104],"an":[105],"advanced":[106],"45nm":[107],"bulk":[108],"CMOS":[109],"fabrication":[110],"process.":[111]},"counts_by_year":[],"updated_date":"2026-07-02T09:51:11.867554","created_date":"2025-10-10T00:00:00"}
