{"id":"https://openalex.org/W2008553099","doi":"https://doi.org/10.1145/2591513.2591588","title":"A study on the use of parallel wiring techniques for sub-20nm designs","display_name":"A study on the use of parallel wiring techniques for sub-20nm designs","publication_year":2014,"publication_date":"2014-05-20","ids":{"openalex":"https://openalex.org/W2008553099","doi":"https://doi.org/10.1145/2591513.2591588","mag":"2008553099"},"language":"en","primary_location":{"id":"doi:10.1145/2591513.2591588","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2591513.2591588","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 24th edition of the great lakes symposium on VLSI","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5014892277","display_name":"Rickard Ewetz","orcid":"https://orcid.org/0000-0002-4183-6926"},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Rickard Ewetz","raw_affiliation_strings":["Purdue University, West Lafayette, IN, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Purdue University, West Lafayette, IN, USA","institution_ids":["https://openalex.org/I219193219"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100429113","display_name":"Wenhao Liu","orcid":"https://orcid.org/0000-0002-8498-9295"},"institutions":[{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Wen-Hao Liu","raw_affiliation_strings":["Cadence Design Systems, Hsinchu, Taiwan Roc","Cadence Design Systems, Hsinchu, Taiwan Roc#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Cadence Design Systems, Hsinchu, Taiwan Roc","institution_ids":[]},{"raw_affiliation_string":"Cadence Design Systems, Hsinchu, Taiwan Roc#TAB#","institution_ids":["https://openalex.org/I66217453"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061862022","display_name":"Kai-Yuan Chao","orcid":"https://orcid.org/0009-0006-1057-1319"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kai-Yuan Chao","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA","Intel Corporation, , Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation, , Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5073705099","display_name":"Ting-Chi Wang","orcid":"https://orcid.org/0000-0002-3435-0418"},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Ting-Chi Wang","raw_affiliation_strings":["National Tsing Hua University, Hsinchu, Taiwan Roc","National Tsing-Hua University, Hsinchu, Taiwan, ROC#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National Tsing Hua University, Hsinchu, Taiwan Roc","institution_ids":["https://openalex.org/I25846049"]},{"raw_affiliation_string":"National Tsing-Hua University, Hsinchu, Taiwan, ROC#TAB#","institution_ids":["https://openalex.org/I25846049"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5110204557","display_name":"Cheng\u2010Kok Koh","orcid":null},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Cheng-Kok Koh","raw_affiliation_strings":["Purdue University, West Lafayette, IN, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Purdue University, West Lafayette, IN, USA","institution_ids":["https://openalex.org/I219193219"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"129","last_page":"134"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/sizing","display_name":"Sizing","score":0.8398076295852661},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.6837024688720703},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6159316897392273},{"id":"https://openalex.org/keywords/network-routing","display_name":"Network routing","score":0.5321007966995239},{"id":"https://openalex.org/keywords/parasitic-extraction","display_name":"Parasitic extraction","score":0.5260577201843262},{"id":"https://openalex.org/keywords/integrated-circuit-layout","display_name":"Integrated circuit layout","score":0.4401320219039917},{"id":"https://openalex.org/keywords/net","display_name":"Net (polyhedron)","score":0.4272039532661438},{"id":"https://openalex.org/keywords/lithography","display_name":"Lithography","score":0.41718292236328125},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.41470208764076233},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.37114351987838745},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.22764801979064941},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2136664092540741},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.18513813614845276},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.17096614837646484},{"id":"https://openalex.org/keywords/optoelectronics","display_name":"Optoelectronics","score":0.07870632410049438}],"concepts":[{"id":"https://openalex.org/C2777767291","wikidata":"https://www.wikidata.org/wiki/Q1080291","display_name":"Sizing","level":2,"score":0.8398076295852661},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.6837024688720703},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6159316897392273},{"id":"https://openalex.org/C2983435990","wikidata":"https://www.wikidata.org/wiki/Q22725","display_name":"Network routing","level":3,"score":0.5321007966995239},{"id":"https://openalex.org/C159818811","wikidata":"https://www.wikidata.org/wiki/Q7135947","display_name":"Parasitic extraction","level":2,"score":0.5260577201843262},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.4401320219039917},{"id":"https://openalex.org/C14166107","wikidata":"https://www.wikidata.org/wiki/Q253829","display_name":"Net (polyhedron)","level":2,"score":0.4272039532661438},{"id":"https://openalex.org/C204223013","wikidata":"https://www.wikidata.org/wiki/Q133036","display_name":"Lithography","level":2,"score":0.41718292236328125},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.41470208764076233},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.37114351987838745},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.22764801979064941},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2136664092540741},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.18513813614845276},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.17096614837646484},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.07870632410049438},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2591513.2591588","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2591513.2591588","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 24th edition of the great lakes symposium on VLSI","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G4270800166","display_name":null,"funder_award_id":"1292-074","funder_id":"https://openalex.org/F4320306087","funder_display_name":"Semiconductor Research Corporation"},{"id":"https://openalex.org/G611223632","display_name":null,"funder_award_id":"CCF-1065318","funder_id":"https://openalex.org/F4320337387","funder_display_name":"Division of Computing and Communication Foundations"}],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"},{"id":"https://openalex.org/F4320306087","display_name":"Semiconductor Research Corporation","ror":"https://ror.org/047z4n946"},{"id":"https://openalex.org/F4320337387","display_name":"Division of Computing and Communication Foundations","ror":"https://ror.org/01mng8331"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":23,"referenced_works":["https://openalex.org/W1941588787","https://openalex.org/W1972894956","https://openalex.org/W1998859420","https://openalex.org/W2000358180","https://openalex.org/W2008015292","https://openalex.org/W2009296772","https://openalex.org/W2020323308","https://openalex.org/W2040165472","https://openalex.org/W2041950850","https://openalex.org/W2052586721","https://openalex.org/W2053902150","https://openalex.org/W2059199163","https://openalex.org/W2069656207","https://openalex.org/W2072175262","https://openalex.org/W2087275089","https://openalex.org/W2110811521","https://openalex.org/W2120599026","https://openalex.org/W2157089032","https://openalex.org/W2159765568","https://openalex.org/W2160252016","https://openalex.org/W2162683631","https://openalex.org/W2171879949","https://openalex.org/W2614175313"],"related_works":["https://openalex.org/W85694287","https://openalex.org/W2885948601","https://openalex.org/W4241171805","https://openalex.org/W2020253769","https://openalex.org/W2143930978","https://openalex.org/W4239381562","https://openalex.org/W2131154858","https://openalex.org/W2086270490","https://openalex.org/W2361901082","https://openalex.org/W2136848459"],"abstract_inverted_index":{"Wire":[0],"sizing":[1,96],"can":[2,104,116],"be":[3,27,105,117],"used":[4,59],"to":[5,60,68],"reduce":[6],"the":[7,15,33,46,49,62,81],"delays":[8],"of":[9,14,32,48],"critical":[10],"nets.":[11],"However,":[12],"because":[13,31],"forbidden":[16],"pitch":[17],"issue":[18],"in":[19,53,121],"sub-20nm":[20,126],"designs,":[21],"wide":[22,75,102],"wires":[23,57,100,103],"may":[24],"no":[25],"longer":[26],"an":[28,66],"attractive":[29],"solution":[30],"restrictive":[34],"wire":[35,95],"spacing":[36],"requirement":[37],"from":[38],"advanced":[39],"lithography.":[40],"In":[41,77],"this":[42],"work,":[43],"we":[44,79],"investigate":[45],"suitability":[47],"parallel":[50,56,99,114],"wiring":[51,115],"technique,":[52],"which":[54],"multiple":[55],"are":[58,112],"route":[61],"same":[63],"net,":[64],"as":[65],"alternative":[67],"routing":[69,89],"a":[70,73,118],"net":[71],"using":[72,97],"single":[74],"wire.":[76],"particular,":[78],"study":[80,92],"trade":[82],"offs":[83],"between":[84],"parasitics,":[85],"timing,":[86],"power,":[87],"and":[88,101],"resources.":[90],"Our":[91],"reveals":[93],"that":[94],"both":[98],"advantageous.":[106],"Moreover,":[107],"if":[108],"high":[109],"layout":[110],"densities":[111],"required,":[113],"viable":[119],"approach":[120],"solving":[122],"timing":[123],"problems":[124],"for":[125],"designs.":[127]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2017,"cited_by_count":2}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
