{"id":"https://openalex.org/W2126061723","doi":"https://doi.org/10.1145/2591513.2591583","title":"Variability-aware design of double gate FinFET-based current mirrors","display_name":"Variability-aware design of double gate FinFET-based current mirrors","publication_year":2014,"publication_date":"2014-05-20","ids":{"openalex":"https://openalex.org/W2126061723","doi":"https://doi.org/10.1145/2591513.2591583","mag":"2126061723"},"language":"en","primary_location":{"id":"doi:10.1145/2591513.2591583","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2591513.2591583","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 24th edition of the great lakes symposium on VLSI","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5065315664","display_name":"Dhruva Ghai","orcid":"https://orcid.org/0000-0002-8204-6330"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Dhruva Ghai","raw_affiliation_strings":["Oriental University, Indore, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Oriental University, Indore, India","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5070359867","display_name":"Saraju P. Mohanty","orcid":"https://orcid.org/0000-0003-2959-6541"},"institutions":[{"id":"https://openalex.org/I123534392","display_name":"University of North Texas","ror":"https://ror.org/00v97ad02","country_code":"US","type":"education","lineage":["https://openalex.org/I123534392"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Saraju Mohanty","raw_affiliation_strings":["University of North Texas, Denton, TX, USA","University of North Texas, Denton, TX, USA#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of North Texas, Denton, TX, USA","institution_ids":["https://openalex.org/I123534392"]},{"raw_affiliation_string":"University of North Texas, Denton, TX, USA#TAB#","institution_ids":["https://openalex.org/I123534392"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5008702299","display_name":"Garima Thakral","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Garima Thakral","raw_affiliation_strings":["Oriental University, Indore, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Oriental University, Indore, India","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5009967108","display_name":"Oghenekarho Okobiah","orcid":null},"institutions":[{"id":"https://openalex.org/I123534392","display_name":"University of North Texas","ror":"https://ror.org/00v97ad02","country_code":"US","type":"education","lineage":["https://openalex.org/I123534392"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Oghenekarho Okobiah","raw_affiliation_strings":["University of North Texas, Denton, TX, USA","University of North Texas, Denton, TX, USA#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of North Texas, Denton, TX, USA","institution_ids":["https://openalex.org/I123534392"]},{"raw_affiliation_string":"University of North Texas, Denton, TX, USA#TAB#","institution_ids":["https://openalex.org/I123534392"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.2237,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.7786088,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"347","last_page":"352"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/current-mirror","display_name":"Current mirror","score":0.8920896053314209},{"id":"https://openalex.org/keywords/mirroring","display_name":"Mirroring","score":0.7257484793663025},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5339100956916809},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5207552909851074},{"id":"https://openalex.org/keywords/current","display_name":"Current (fluid)","score":0.5184828639030457},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.503438413143158},{"id":"https://openalex.org/keywords/silicon-on-insulator","display_name":"Silicon on insulator","score":0.49378809332847595},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.4932219386100769},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.49255022406578064},{"id":"https://openalex.org/keywords/mosfet","display_name":"MOSFET","score":0.4878695011138916},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.47074609994888306},{"id":"https://openalex.org/keywords/biasing","display_name":"Biasing","score":0.4670286178588867},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.43500664830207825},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.36507880687713623},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.342316210269928},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.21914783120155334},{"id":"https://openalex.org/keywords/optoelectronics","display_name":"Optoelectronics","score":0.18833771347999573},{"id":"https://openalex.org/keywords/silicon","display_name":"Silicon","score":0.0960974395275116}],"concepts":[{"id":"https://openalex.org/C173966970","wikidata":"https://www.wikidata.org/wiki/Q786012","display_name":"Current mirror","level":4,"score":0.8920896053314209},{"id":"https://openalex.org/C189645446","wikidata":"https://www.wikidata.org/wiki/Q350865","display_name":"Mirroring","level":2,"score":0.7257484793663025},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5339100956916809},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5207552909851074},{"id":"https://openalex.org/C148043351","wikidata":"https://www.wikidata.org/wiki/Q4456944","display_name":"Current (fluid)","level":2,"score":0.5184828639030457},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.503438413143158},{"id":"https://openalex.org/C53143962","wikidata":"https://www.wikidata.org/wiki/Q1478788","display_name":"Silicon on insulator","level":3,"score":0.49378809332847595},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.4932219386100769},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.49255022406578064},{"id":"https://openalex.org/C2778413303","wikidata":"https://www.wikidata.org/wiki/Q210793","display_name":"MOSFET","level":4,"score":0.4878695011138916},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.47074609994888306},{"id":"https://openalex.org/C20254490","wikidata":"https://www.wikidata.org/wiki/Q719550","display_name":"Biasing","level":3,"score":0.4670286178588867},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.43500664830207825},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.36507880687713623},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.342316210269928},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.21914783120155334},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.18833771347999573},{"id":"https://openalex.org/C544956773","wikidata":"https://www.wikidata.org/wiki/Q670","display_name":"Silicon","level":2,"score":0.0960974395275116},{"id":"https://openalex.org/C144024400","wikidata":"https://www.wikidata.org/wiki/Q21201","display_name":"Sociology","level":0,"score":0.0},{"id":"https://openalex.org/C46312422","wikidata":"https://www.wikidata.org/wiki/Q11024","display_name":"Communication","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2591513.2591583","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2591513.2591583","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 24th edition of the great lakes symposium on VLSI","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.5199999809265137}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W1597620877","https://openalex.org/W1698001179","https://openalex.org/W1846563663","https://openalex.org/W1970755039","https://openalex.org/W2006440698","https://openalex.org/W2017842294","https://openalex.org/W2033700531","https://openalex.org/W2040511447","https://openalex.org/W2052145319","https://openalex.org/W2091893572","https://openalex.org/W2104781003","https://openalex.org/W2112475735","https://openalex.org/W2113766915","https://openalex.org/W2130249349","https://openalex.org/W2134162576","https://openalex.org/W2141415096","https://openalex.org/W2145474418","https://openalex.org/W2150368362","https://openalex.org/W2152404163","https://openalex.org/W2158880602","https://openalex.org/W2531972392","https://openalex.org/W4231501498"],"related_works":["https://openalex.org/W2160122484","https://openalex.org/W2184860653","https://openalex.org/W1992627288","https://openalex.org/W2167134364","https://openalex.org/W2217307244","https://openalex.org/W2350431618","https://openalex.org/W2124484215","https://openalex.org/W2111968304","https://openalex.org/W1923914176","https://openalex.org/W1990582614"],"abstract_inverted_index":{"With":[0],"the":[1,18,36,69,94,126,133],"technology":[2],"trend":[3],"moving":[4],"towards":[5],"smaller":[6],"geometries":[7],"and":[8,62,119],"improved":[9],"circuit":[10],"performances,":[11],"multigate":[12],"transistors":[13],"are":[14,130],"expected":[15],"to":[16,27],"replace":[17],"traditional":[19],"bulk":[20],"devices.":[21],"The":[22],"double-gate":[23],"FinFET":[24],"lends":[25],"itself":[26],"a":[28,43,75],"rich":[29],"design":[30,46,59,85,138],"space":[31],"using":[32,139],"various":[33],"configurations":[34,73],"of":[35,71,74,86],"two":[37],"gates.":[38],"Accurate":[39],"current":[40,64,87,98,136],"mirroring":[41],"is":[42,53,110],"critical":[44],"analog":[45,58],"requirement":[47],"in":[48,57],"many":[49],"applications.":[50],"Current":[51],"mirror":[52,88,99,137],"an":[54],"essential":[55],"component":[56],"for":[60,83,132,135],"biasing":[61],"constant":[63],"generation.":[65],"This":[66],"paper":[67],"presents":[68],"exploration":[70],"different":[72],"double":[76],"gate":[77],"fully":[78],"depleted":[79],"SOI":[80],"based":[81],"FinFETs":[82],"efficient":[84],"designs.":[89],"In":[90],"particular,":[91],"comparison":[92],"among":[93],"important":[95],"Figures-of-Merit":[96],"(FoMs)":[97],"designs":[100],"including":[101],"mismatch,":[102],"variability,":[103],"output":[104],"resistance":[105],"($r_0$),":[106],"compliance":[107],"voltage":[108],"($V_{CV}$)":[109],"presented":[111,131],"for:":[112],"(1)":[113],"shorted-gate":[114],"(SG),":[115],"(2)":[116],"independent-gate":[117],"(IG),":[118],"(3)":[120],"low-power":[121],"(LP)":[122],"configurations.":[123],"Based":[124],"on":[125],"results":[127],"obtained,":[128],"guidelines":[129],"designer":[134],"FinFET.":[140]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}