{"id":"https://openalex.org/W1968073476","doi":"https://doi.org/10.1145/2591513.2591536","title":"A complete electronic network interface architecture for global contention-free communication over emerging optical networks-on-chip","display_name":"A complete electronic network interface architecture for global contention-free communication over emerging optical networks-on-chip","publication_year":2014,"publication_date":"2014-05-20","ids":{"openalex":"https://openalex.org/W1968073476","doi":"https://doi.org/10.1145/2591513.2591536","mag":"1968073476"},"language":"en","primary_location":{"id":"doi:10.1145/2591513.2591536","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2591513.2591536","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 24th edition of the great lakes symposium on VLSI","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5009215171","display_name":"Marta Ort\u00edn","orcid":"https://orcid.org/0000-0003-3161-3793"},"institutions":[{"id":"https://openalex.org/I255234318","display_name":"Universidad de Zaragoza","ror":"https://ror.org/012a91z28","country_code":"ES","type":"education","lineage":["https://openalex.org/I255234318"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Marta Ort\u00edn-Ob\u00f3n","raw_affiliation_strings":["University of Zaragoza, Zaragoza, Spain","University of Zaragoza, Zaragoza (Spain)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Zaragoza, Zaragoza, Spain","institution_ids":["https://openalex.org/I255234318"]},{"raw_affiliation_string":"University of Zaragoza, Zaragoza (Spain)","institution_ids":["https://openalex.org/I255234318"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5044730358","display_name":"Luca Ramini","orcid":null},"institutions":[{"id":"https://openalex.org/I201324441","display_name":"University of Ferrara","ror":"https://ror.org/041zkgm14","country_code":"IT","type":"education","lineage":["https://openalex.org/I201324441"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Luca Ramini","raw_affiliation_strings":["University of Ferrara, Ferrara, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Ferrara, Ferrara, Italy","institution_ids":["https://openalex.org/I201324441"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5051767719","display_name":"Herv\u00e9 Tatenguem","orcid":"https://orcid.org/0000-0003-0600-2958"},"institutions":[{"id":"https://openalex.org/I201324441","display_name":"University of Ferrara","ror":"https://ror.org/041zkgm14","country_code":"IT","type":"education","lineage":["https://openalex.org/I201324441"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Herve Tatenguem Fankem","raw_affiliation_strings":["University of Ferrara, Ferrara, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Ferrara, Ferrara, Italy","institution_ids":["https://openalex.org/I201324441"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5050160407","display_name":"V\u00edctor Vi\u00f1als","orcid":"https://orcid.org/0000-0002-5976-1352"},"institutions":[{"id":"https://openalex.org/I255234318","display_name":"Universidad de Zaragoza","ror":"https://ror.org/012a91z28","country_code":"ES","type":"education","lineage":["https://openalex.org/I255234318"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"V\u00edctor Vi\u00f1als","raw_affiliation_strings":["University of Zaragoza, Zaragoza, Spain","University of Zaragoza, Zaragoza (Spain)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Zaragoza, Zaragoza, Spain","institution_ids":["https://openalex.org/I255234318"]},{"raw_affiliation_string":"University of Zaragoza, Zaragoza (Spain)","institution_ids":["https://openalex.org/I255234318"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5011268330","display_name":"Davide Bertozzi","orcid":"https://orcid.org/0000-0001-7462-4551"},"institutions":[{"id":"https://openalex.org/I201324441","display_name":"University of Ferrara","ror":"https://ror.org/041zkgm14","country_code":"IT","type":"education","lineage":["https://openalex.org/I201324441"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Davide Bertozzi","raw_affiliation_strings":["University of Ferrara, Ferrara, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Ferrara, Ferrara, Italy","institution_ids":["https://openalex.org/I201324441"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.1039,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.73455378,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"267","last_page":"272"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10847","display_name":"Advanced Optical Network Technologies","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10299","display_name":"Photonic and Optical Devices","score":0.9958000183105469,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/serialization","display_name":"Serialization","score":0.8089932203292847},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7567218542098999},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.6271802186965942},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.5262783169746399},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.49861907958984375},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4394628405570984},{"id":"https://openalex.org/keywords/deadlock","display_name":"Deadlock","score":0.4332406520843506},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.416089802980423},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.41179144382476807},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.13645827770233154},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.10223302245140076}],"concepts":[{"id":"https://openalex.org/C52723943","wikidata":"https://www.wikidata.org/wiki/Q1127410","display_name":"Serialization","level":2,"score":0.8089932203292847},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7567218542098999},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.6271802186965942},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.5262783169746399},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.49861907958984375},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4394628405570984},{"id":"https://openalex.org/C159023740","wikidata":"https://www.wikidata.org/wiki/Q623276","display_name":"Deadlock","level":2,"score":0.4332406520843506},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.416089802980423},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.41179144382476807},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.13645827770233154},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.10223302245140076},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/2591513.2591536","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2591513.2591536","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 24th edition of the great lakes symposium on VLSI","raw_type":"proceedings-article"},{"id":"pmh:oai:iris.unife.it:11392/2334590","is_oa":false,"landing_page_url":"http://hdl.handle.net/11392/2334590","pdf_url":null,"source":{"id":"https://openalex.org/S4306400369","display_name":"Institutional Research Information System University of Ferrara (University of Ferrara)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I201324441","host_organization_name":"University of Ferrara","host_organization_lineage":["https://openalex.org/I201324441"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.6100000143051147}],"awards":[{"id":"https://openalex.org/G4372568702","display_name":null,"funder_award_id":"217068","funder_id":"https://openalex.org/F4320334960","funder_display_name":"Seventh Framework Programme"},{"id":"https://openalex.org/G7124724614","display_name":null,"funder_award_id":"RBFR08LE6V","funder_id":"https://openalex.org/F4320321873","funder_display_name":"Ministero dell\u2019Istruzione, dell\u2019Universit\u00e0 e della Ricerca"}],"funders":[{"id":"https://openalex.org/F4320321873","display_name":"Ministero dell\u2019Istruzione, dell\u2019Universit\u00e0 e della Ricerca","ror":"https://ror.org/0166hxq48"},{"id":"https://openalex.org/F4320334960","display_name":"Seventh Framework Programme","ror":"https://ror.org/00k4n6c32"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W1501077214","https://openalex.org/W1538452085","https://openalex.org/W1600358781","https://openalex.org/W1966613663","https://openalex.org/W1997086988","https://openalex.org/W1997188504","https://openalex.org/W2080106381","https://openalex.org/W2085836326","https://openalex.org/W2101193087","https://openalex.org/W2104989962","https://openalex.org/W2108082686","https://openalex.org/W2108564112","https://openalex.org/W2119565088","https://openalex.org/W2132456420","https://openalex.org/W2145112046","https://openalex.org/W2145544452","https://openalex.org/W2150018637","https://openalex.org/W2154804393","https://openalex.org/W2161380643","https://openalex.org/W2164846625","https://openalex.org/W2171721604","https://openalex.org/W4256238177"],"related_works":["https://openalex.org/W4231356583","https://openalex.org/W1593760324","https://openalex.org/W2376159383","https://openalex.org/W2351439380","https://openalex.org/W2751820975","https://openalex.org/W4863605","https://openalex.org/W4285287318","https://openalex.org/W4400409835","https://openalex.org/W2784141701","https://openalex.org/W1978899622"],"abstract_inverted_index":{"Although":[0],"many":[1],"valuable":[2],"research":[3],"works":[4],"have":[5],"investigated":[6],"the":[7,13,23,34,66,72,80,92],"properties":[8],"of":[9,16,22,39,49,94],"optical":[10,31,87],"networks-on-chip":[11],"(ONoCs),":[12],"vast":[14],"majority":[15],"them":[17],"lack":[18],"an":[19],"accurate":[20],"exploration":[21],"network":[24],"interface":[25],"architecture":[26,41,84],"(NI)":[27],"required":[28],"to":[29],"support":[30],"communications":[32],"on":[33],"silicon":[35],"chip.":[36],"The":[37],"complexity":[38,68],"this":[40,77],"is":[42,69],"especially":[43],"critical":[44],"for":[45,85],"a":[46,54,113],"specific":[47],"kind":[48],"ONoCs:":[50],"wavelength-routed":[51,86],"ones.":[52],"From":[53],"logical":[55],"viewpoint,":[56],"they":[57],"can":[58],"be":[59],"considered":[60],"as":[61,98],"full":[62],"nonblocking":[63],"crossbars,":[64],"thus":[65],"control":[67],"implemented":[70],"at":[71],"NIs.":[73],"To":[74],"our":[75],"knowledge,":[76],"paper":[78],"proposes":[79],"first":[81],"complete":[82,114],"NI":[83],"NoCs,":[88],"by":[89],"coping":[90],"with":[91,109],"intricacy":[93],"networking":[95],"issues":[96],"such":[97],"flow":[99],"control,":[100],"buffering":[101],"strategy,":[102],"deadlock":[103],"avoidance,":[104],"serialization,":[105],"and":[106],"above":[107],"all,":[108],"their":[110],"codesign":[111],"in":[112],"architecture.":[115]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":2}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2016-06-24T00:00:00"}
