{"id":"https://openalex.org/W1966105387","doi":"https://doi.org/10.1145/2566668","title":"Accelerating FPGA debug","display_name":"Accelerating FPGA debug","publication_year":2014,"publication_date":"2014-03-01","ids":{"openalex":"https://openalex.org/W1966105387","doi":"https://doi.org/10.1145/2566668","mag":"1966105387"},"language":"en","primary_location":{"id":"doi:10.1145/2566668","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2566668","pdf_url":null,"source":{"id":"https://openalex.org/S105046310","display_name":"ACM Transactions on Design Automation of Electronic Systems","issn_l":"1084-4309","issn":["1084-4309","1557-7309"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Design Automation of Electronic Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5025451600","display_name":"Eddie Hung","orcid":"https://orcid.org/0000-0001-7670-116X"},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Eddie Hung","raw_affiliation_strings":["University of British Columbia, Vancouver, BC, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of British Columbia, Vancouver, BC, Canada","institution_ids":["https://openalex.org/I141945490"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5013246362","display_name":"Steven J. E. Wilton","orcid":"https://orcid.org/0000-0002-1241-6690"},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Steven J. E. Wilton","raw_affiliation_strings":["University of British Columbia, Vancouver, BC, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of British Columbia, Vancouver, BC, Canada","institution_ids":["https://openalex.org/I141945490"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I141945490"],"apc_list":null,"apc_paid":null,"fwci":1.4503,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.83542031,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":98},"biblio":{"volume":"19","issue":"2","first_page":"1","last_page":"23"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8689905405044556},{"id":"https://openalex.org/keywords/debugging","display_name":"Debugging","score":0.7800018787384033},{"id":"https://openalex.org/keywords/multiplexer","display_name":"Multiplexer","score":0.6873234510421753},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6730913519859314},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6268918514251709},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.5521032214164734},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5173118114471436},{"id":"https://openalex.org/keywords/trace","display_name":"TRACE (psycholinguistics)","score":0.4312880337238312},{"id":"https://openalex.org/keywords/real-time-computing","display_name":"Real-time computing","score":0.33671969175338745},{"id":"https://openalex.org/keywords/multiplexing","display_name":"Multiplexing","score":0.3306315839290619},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.13003405928611755}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8689905405044556},{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.7800018787384033},{"id":"https://openalex.org/C70970002","wikidata":"https://www.wikidata.org/wiki/Q189434","display_name":"Multiplexer","level":3,"score":0.6873234510421753},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6730913519859314},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6268918514251709},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5521032214164734},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5173118114471436},{"id":"https://openalex.org/C75291252","wikidata":"https://www.wikidata.org/wiki/Q1315756","display_name":"TRACE (psycholinguistics)","level":2,"score":0.4312880337238312},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.33671969175338745},{"id":"https://openalex.org/C19275194","wikidata":"https://www.wikidata.org/wiki/Q222903","display_name":"Multiplexing","level":2,"score":0.3306315839290619},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.13003405928611755},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C41895202","wikidata":"https://www.wikidata.org/wiki/Q8162","display_name":"Linguistics","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2566668","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2566668","pdf_url":null,"source":{"id":"https://openalex.org/S105046310","display_name":"ACM Transactions on Design Automation of Electronic Systems","issn_l":"1084-4309","issn":["1084-4309","1557-7309"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Design Automation of Electronic Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W101494604","https://openalex.org/W1971679152","https://openalex.org/W1976150142","https://openalex.org/W2002792327","https://openalex.org/W2032699516","https://openalex.org/W2041871970","https://openalex.org/W2073321629","https://openalex.org/W2088256110","https://openalex.org/W2105993342","https://openalex.org/W2107662612","https://openalex.org/W2124402195","https://openalex.org/W2129547250","https://openalex.org/W2130934470","https://openalex.org/W2138383740","https://openalex.org/W2141261568","https://openalex.org/W2275304190","https://openalex.org/W4250446534","https://openalex.org/W4285719527","https://openalex.org/W6668663246"],"related_works":["https://openalex.org/W2543101158","https://openalex.org/W2993910401","https://openalex.org/W2039899645","https://openalex.org/W1569638199","https://openalex.org/W2258948885","https://openalex.org/W2371342700","https://openalex.org/W2327110311","https://openalex.org/W2363059241","https://openalex.org/W3215187042","https://openalex.org/W266342242"],"abstract_inverted_index":{"FPGA":[0,96],"technology":[1],"is":[2,32,82,91],"commonly":[3],"used":[4],"to":[5,53,73,99,105,116,136,165],"prototype":[6],"new":[7,124,157],"digital":[8],"designs":[9],"before":[10],"entering":[11],"fabrication.":[12],"Whilst":[13],"these":[14,144],"physical":[15],"prototypes":[16],"can":[17,45,133,172],"operate":[18],"many":[19,186],"orders":[20],"of":[21,35,58,69,121,143,163,167],"magnitude":[22],"faster":[23],"than":[24,177],"through":[25,104],"a":[26,29,55,123,181],"logic":[27],"simulator,":[28],"fundamental":[30],"limitation":[31],"their":[33,75],"lack":[34],"on-chip":[36],"visibility":[37],"when":[38],"debugging.":[39],"To":[40],"counter":[41],"this,":[42],"trace-buffer-based":[43],"instrumentation":[44],"be":[46,173],"installed":[47],"into":[48],"the":[49,71,80,106,138,168],"prototype,":[50],"allowing":[51],"designers":[52,112],"capture":[54],"predetermined":[56],"window":[57,81],"signal":[59],"data":[60],"during":[61,110],"live":[62],"operation":[63],"for":[64,180,193],"offline":[65],"analysis.":[66],"However,":[67],"instead":[68,120],"requiring":[70],"designer":[72],"recompile":[74],"entire":[76],"circuit":[77,102],"every":[78],"time":[79],"modified,":[83],"this":[84,118,131],"article":[85],"proposes":[86],"that":[87,156],"an":[88],"overlay":[89],"network":[90,119,132,158],"constructed":[92],"using":[93,150],"only":[94,114],"spare":[95],"routing":[97],"multiplexers":[98],"connect":[100],"all":[101],"signals":[103,135,164],"trace":[107,141],"instruments.":[108],"Thus,":[109],"debugging,":[111],"would":[113],"need":[115],"reconfigure":[117],"finding":[122],"place-and-route":[125],"solution.":[126],"Furthermore,":[127],"we":[128],"describe":[129],"how":[130],"deliver":[134],"both":[137],"trigger":[139],"and":[140],"units":[142],"instruments,":[145],"which":[146],"are":[147],"implemented":[148],"simultaneously":[149],"dual-port":[151],"RAMs.":[152],"Our":[153,190],"results":[154],"show":[155],"configurations":[159],"connecting":[160],"any":[161],"subset":[162],"80--90%":[166],"available":[169,192],"RAM":[170],"capacity":[171],"computed":[174],"in":[175],"less":[176],"70":[178],"seconds,":[179],"100,000":[182],"LUT":[183],"circuit,":[184],"as":[185,188],"times":[187],"necessary.":[189],"tool\u2014QuickTrace\u2014is":[191],"download.":[194]},"counts_by_year":[{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":2},{"year":2015,"cited_by_count":5}],"updated_date":"2026-05-21T06:26:12.895304","created_date":"2025-10-10T00:00:00"}
