{"id":"https://openalex.org/W2085585890","doi":"https://doi.org/10.1145/2556857.2556859","title":"A feature-rich NoC switch with cross-feature optimizations for the next generation of reliable and reconfigurable embedded systems","display_name":"A feature-rich NoC switch with cross-feature optimizations for the next generation of reliable and reconfigurable embedded systems","publication_year":2014,"publication_date":"2014-01-14","ids":{"openalex":"https://openalex.org/W2085585890","doi":"https://doi.org/10.1145/2556857.2556859","mag":"2085585890"},"language":"en","primary_location":{"id":"doi:10.1145/2556857.2556859","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2556857.2556859","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 8th International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5027446961","display_name":"Alessandro Strano","orcid":null},"institutions":[{"id":"https://openalex.org/I201324441","display_name":"University of Ferrara","ror":"https://ror.org/041zkgm14","country_code":"IT","type":"education","lineage":["https://openalex.org/I201324441"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Alessandro Strano","raw_affiliation_strings":["ENDIF, University of Ferrara, Ferrara, Italy"],"affiliations":[{"raw_affiliation_string":"ENDIF, University of Ferrara, Ferrara, Italy","institution_ids":["https://openalex.org/I201324441"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5037565685","display_name":"Alberto Ghiribaldi","orcid":null},"institutions":[{"id":"https://openalex.org/I201324441","display_name":"University of Ferrara","ror":"https://ror.org/041zkgm14","country_code":"IT","type":"education","lineage":["https://openalex.org/I201324441"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Alberto Ghiribaldi","raw_affiliation_strings":["ENDIF, University of Ferrara, Ferrara, Italy"],"affiliations":[{"raw_affiliation_string":"ENDIF, University of Ferrara, Ferrara, Italy","institution_ids":["https://openalex.org/I201324441"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5051767719","display_name":"Herv\u00e9 Tatenguem","orcid":"https://orcid.org/0000-0003-0600-2958"},"institutions":[{"id":"https://openalex.org/I201324441","display_name":"University of Ferrara","ror":"https://ror.org/041zkgm14","country_code":"IT","type":"education","lineage":["https://openalex.org/I201324441"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Herve Tatenguem Fankem","raw_affiliation_strings":["ENDIF, University of Ferrara, Ferrara, Italy"],"affiliations":[{"raw_affiliation_string":"ENDIF, University of Ferrara, Ferrara, Italy","institution_ids":["https://openalex.org/I201324441"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5011268330","display_name":"Davide Bertozzi","orcid":"https://orcid.org/0000-0001-7462-4551"},"institutions":[{"id":"https://openalex.org/I201324441","display_name":"University of Ferrara","ror":"https://ror.org/041zkgm14","country_code":"IT","type":"education","lineage":["https://openalex.org/I201324441"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Davide Bertozzi","raw_affiliation_strings":["ENDIF, University of Ferrara, Ferrara, Italy"],"affiliations":[{"raw_affiliation_string":"ENDIF, University of Ferrara, Ferrara, Italy","institution_ids":["https://openalex.org/I201324441"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5027446961"],"corresponding_institution_ids":["https://openalex.org/I201324441"],"apc_list":null,"apc_paid":null,"fwci":0.7195,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.76575326,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9976000189781189,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7624669075012207},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5750693082809448},{"id":"https://openalex.org/keywords/feature","display_name":"Feature (linguistics)","score":0.5508308410644531},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5449820756912231},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.49573051929473877},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.4502784013748169},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.44877398014068604},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.43447816371917725},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.4276340901851654},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.18690559267997742}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7624669075012207},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5750693082809448},{"id":"https://openalex.org/C2776401178","wikidata":"https://www.wikidata.org/wiki/Q12050496","display_name":"Feature (linguistics)","level":2,"score":0.5508308410644531},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5449820756912231},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.49573051929473877},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.4502784013748169},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.44877398014068604},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.43447816371917725},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.4276340901851654},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.18690559267997742},{"id":"https://openalex.org/C41895202","wikidata":"https://www.wikidata.org/wiki/Q8162","display_name":"Linguistics","level":1,"score":0.0},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2556857.2556859","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2556857.2556859","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 8th International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.5400000214576721,"display_name":"Industry, innovation and infrastructure"}],"awards":[{"id":"https://openalex.org/G7642821367","display_name":null,"funder_award_id":"FP7-ICT-288574","funder_id":"https://openalex.org/F4320334960","funder_display_name":"Seventh Framework Programme"}],"funders":[{"id":"https://openalex.org/F4320334960","display_name":"Seventh Framework Programme","ror":"https://ror.org/00k4n6c32"},{"id":"https://openalex.org/F4320338370","display_name":"FP7 Information and Communication Technologies","ror":null}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W147650083","https://openalex.org/W387539198","https://openalex.org/W1600358781","https://openalex.org/W1978523342","https://openalex.org/W2057785859","https://openalex.org/W2073742560","https://openalex.org/W2079457862","https://openalex.org/W2091853270","https://openalex.org/W2111448960","https://openalex.org/W2113404195"],"related_works":["https://openalex.org/W2364531466","https://openalex.org/W2383828164","https://openalex.org/W2148971169","https://openalex.org/W396164270","https://openalex.org/W2046114918","https://openalex.org/W2754086592","https://openalex.org/W3198758847","https://openalex.org/W4230458348","https://openalex.org/W1591122270","https://openalex.org/W2063558432"],"abstract_inverted_index":{"The":[0,39,75],"digital":[1],"design":[2,47,103],"convergence,":[3],"together":[4],"with":[5],"the":[6,15,34,46,49,57,63,79,102,112,116],"new":[7,19],"usage":[8],"models":[9],"of":[10,48,90,105,119],"mobile":[11],"devices,":[12],"are":[13],"raising":[14],"clear":[16],"need":[17],"for":[18,78,115],"requirements":[20],"such":[21,30],"as":[22,111],"flexible":[23],"partitioning,":[24],"runtime":[25,72],"adaptivity,":[26],"reliability.":[27],"In":[28],"turn,":[29],"feature-rich":[31],"architectures":[32],"make":[33],"testing":[35],"challenge":[36,77,99],"more":[37],"severe.":[38],"above":[40],"trend":[41],"has":[42],"direct":[43],"implications":[44],"on":[45,97],"underlying":[50],"on-chip":[51],"network,":[52],"which":[53],"becomes":[54],"not":[55],"only":[56],"system":[58],"integration":[59],"framework,":[60],"but":[61],"also":[62],"control":[64],"framework":[65],"executing":[66],"hypervisor":[67],"commands,":[68],"or":[69],"reacting":[70],"to":[71,82],"operating":[73],"conditions.":[74],"ultimate":[76],"NoC":[80,107],"is":[81],"co-design":[83],"these":[84],"features":[85],"together,":[86],"while":[87],"taking":[88],"advantage":[89],"cross-feature":[91],"optimization":[92],"opportunities.":[93],"This":[94],"paper":[95],"takes":[96],"this":[98],"and":[100,121],"illustrates":[101],"experience":[104],"a":[106],"switch":[108],"architecture":[109],"serving":[110],"key":[113],"enabler":[114],"next":[117],"generation":[118],"reliable":[120],"reconfigurable":[122],"systems.":[123]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2017,"cited_by_count":2}],"updated_date":"2026-04-17T18:11:37.981687","created_date":"2025-10-10T00:00:00"}