{"id":"https://openalex.org/W1985126867","doi":"https://doi.org/10.1145/2554688.2554752","title":"Optimally mitigating BTI-induced FPGA device aging with discriminative voltage scaling (abstract only)","display_name":"Optimally mitigating BTI-induced FPGA device aging with discriminative voltage scaling (abstract only)","publication_year":2014,"publication_date":"2014-02-18","ids":{"openalex":"https://openalex.org/W1985126867","doi":"https://doi.org/10.1145/2554688.2554752","mag":"1985126867"},"language":"en","primary_location":{"id":"doi:10.1145/2554688.2554752","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2554688.2554752","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays","raw_type":"proceedings-article"},"type":"conference-abstract","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5018409371","display_name":"Yu Bai","orcid":"https://orcid.org/0000-0002-2303-1120"},"institutions":[{"id":"https://openalex.org/I106165777","display_name":"University of Central Florida","ror":"https://ror.org/036nfer12","country_code":"US","type":"education","lineage":["https://openalex.org/I106165777"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yu Bai","raw_affiliation_strings":["University of Central Florida, Orlando, FL, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Central Florida, Orlando, FL, USA","institution_ids":["https://openalex.org/I106165777"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5079607802","display_name":"Mohammed Alawad","orcid":"https://orcid.org/0000-0002-7491-0440"},"institutions":[{"id":"https://openalex.org/I106165777","display_name":"University of Central Florida","ror":"https://ror.org/036nfer12","country_code":"US","type":"education","lineage":["https://openalex.org/I106165777"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mohammed Alawad","raw_affiliation_strings":["University of Central Florida, Orlando, FL, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Central Florida, Orlando, FL, USA","institution_ids":["https://openalex.org/I106165777"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5060908808","display_name":"Mingjie Lin","orcid":"https://orcid.org/0000-0002-3225-4406"},"institutions":[{"id":"https://openalex.org/I106165777","display_name":"University of Central Florida","ror":"https://ror.org/036nfer12","country_code":"US","type":"education","lineage":["https://openalex.org/I106165777"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mingjie Lin","raw_affiliation_strings":["University of Central Florida, Orlando, FL, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Central Florida, Orlando, FL, USA","institution_ids":["https://openalex.org/I106165777"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I106165777"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"246","last_page":"246"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9975000023841858,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7644712924957275},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.6808398365974426},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.6536740064620972},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6472505331039429},{"id":"https://openalex.org/keywords/modular-design","display_name":"Modular design","score":0.5691261887550354},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5059589743614197},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.46998775005340576},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.46793171763420105},{"id":"https://openalex.org/keywords/node","display_name":"Node (physics)","score":0.446296751499176},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.42727744579315186},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4173589050769806},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.40470802783966064},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.32985830307006836},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19509312510490417},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.19352054595947266},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.1479138433933258}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7644712924957275},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.6808398365974426},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.6536740064620972},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6472505331039429},{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.5691261887550354},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5059589743614197},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.46998775005340576},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.46793171763420105},{"id":"https://openalex.org/C62611344","wikidata":"https://www.wikidata.org/wiki/Q1062658","display_name":"Node (physics)","level":2,"score":0.446296751499176},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.42727744579315186},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4173589050769806},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.40470802783966064},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.32985830307006836},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19509312510490417},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.19352054595947266},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.1479138433933258},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0},{"id":"https://openalex.org/C66938386","wikidata":"https://www.wikidata.org/wiki/Q633538","display_name":"Structural engineering","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2554688.2554752","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2554688.2554752","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.8799999952316284}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W629811444","https://openalex.org/W2170979950","https://openalex.org/W1900707063","https://openalex.org/W2991739378","https://openalex.org/W1980349267","https://openalex.org/W2098419840","https://openalex.org/W2140610743","https://openalex.org/W2116326546","https://openalex.org/W2097637358","https://openalex.org/W2151104031"],"abstract_inverted_index":{"With":[0],"the":[1,7,61,69,82,116,126,134],"CMOS":[2],"technology":[3],"aggressively":[4],"scaling":[5,85],"towards":[6],"22nm":[8],"node,":[9],"modern":[10],"FPGA":[11,53,121],"devices":[12],"face":[13],"tremendous":[14],"aging-":[15],"induced":[16],"reliability":[17,96,118,130],"challenges":[18],"due":[19],"to":[20,59,89,114],"Bias":[21],"Temperature":[22],"In-":[23],"stability":[24],"(BTI)":[25],"and":[26,45,131],"Hot":[27],"Carrier":[28],"Injection":[29],"(HCI).":[30],"This":[31],"paper":[32],"presents":[33],"a":[34],"novel":[35],"antiaging":[36],"technique":[37],"at":[38],"logic":[39],"level":[40],"that":[41],"is":[42,58],"both":[43],"scalable":[44],"applicable":[46],"for":[47],"VLSI":[48],"digital":[49],"circuits":[50],"implemented":[51],"with":[52],"devices.":[54],"The":[55],"key":[56],"idea":[57,83],"prolong":[60],"lifetime":[62],"of":[63,72,84,119],"FPGA-mapped":[64],"designs":[65],"by":[66,105,123],"strategically":[67],"elevating":[68],"VDD":[70,86,135],"values":[71],"some":[73],"LUTs":[74],"based":[75],"on":[76],"their":[77],"modular":[78],"criticality":[79],"values.":[80],"Although":[81],"in":[87],"order":[88],"improve":[90],"either":[91],"energy":[92],"efficiency":[93],"or":[94],"circuit":[95],"has":[97],"been":[98],"explored":[99],"extensively,":[100],"our":[101],"study":[102],"distinguishes":[103],"itself":[104],"approaching":[106],"this":[107],"challenge":[108],"through":[109],"analytical":[110],"procedure,":[111],"therefore":[112],"able":[113],"maximize":[115],"overall":[117],"target":[120],"design":[122],"rigorously":[124],"modelling":[125],"BTI-induce":[127],"de-":[128],"vice":[129],"optimally":[132],"solving":[133],"assignment":[136],"problem.":[137]},"counts_by_year":[],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}