{"id":"https://openalex.org/W2027376338","doi":"https://doi.org/10.1145/2554688.2554740","title":"Coordinating routing resources for hex pips test in island-style FPGAs (abstract only)","display_name":"Coordinating routing resources for hex pips test in island-style FPGAs (abstract only)","publication_year":2014,"publication_date":"2014-02-18","ids":{"openalex":"https://openalex.org/W2027376338","doi":"https://doi.org/10.1145/2554688.2554740","mag":"2027376338"},"language":"en","primary_location":{"id":"doi:10.1145/2554688.2554740","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2554688.2554740","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays","raw_type":"proceedings-article"},"type":"conference-abstract","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100403380","display_name":"Fan Zhang","orcid":"https://orcid.org/0000-0001-6087-8243"},"institutions":[{"id":"https://openalex.org/I4210089056","display_name":"Beijing Microelectronics Technology Institute","ror":"https://ror.org/007y7ej30","country_code":"CN","type":"other","lineage":["https://openalex.org/I4210089056"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Fan Zhang","raw_affiliation_strings":["Beijing Microelectronics Technology Institute, Beijing, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Beijing Microelectronics Technology Institute, Beijing, China","institution_ids":["https://openalex.org/I4210089056"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100671215","display_name":"Lei Chen","orcid":"https://orcid.org/0000-0001-9369-9524"},"institutions":[{"id":"https://openalex.org/I4210089056","display_name":"Beijing Microelectronics Technology Institute","ror":"https://ror.org/007y7ej30","country_code":"CN","type":"other","lineage":["https://openalex.org/I4210089056"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Lei Chen","raw_affiliation_strings":["Beijing Microelectronics Technology Institute, Beijing, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Beijing Microelectronics Technology Institute, Beijing, China","institution_ids":["https://openalex.org/I4210089056"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5035679293","display_name":"Wenyao Xu","orcid":"https://orcid.org/0000-0001-6444-9411"},"institutions":[{"id":"https://openalex.org/I63190737","display_name":"University at Buffalo, State University of New York","ror":"https://ror.org/01y64my43","country_code":"US","type":"education","lineage":["https://openalex.org/I63190737"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Wenyao Xu","raw_affiliation_strings":["University of Buffalo, the State University of New York, Buffalo, NY, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Buffalo, the State University of New York, Buffalo, NY, USA","institution_ids":["https://openalex.org/I63190737"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5030647669","display_name":"Yuanfu Zhao","orcid":"https://orcid.org/0000-0002-6786-6293"},"institutions":[{"id":"https://openalex.org/I4210089056","display_name":"Beijing Microelectronics Technology Institute","ror":"https://ror.org/007y7ej30","country_code":"CN","type":"other","lineage":["https://openalex.org/I4210089056"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yuanfu Zhao","raw_affiliation_strings":["Beijing Microelectronics Technology Institute, Beijing, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Beijing Microelectronics Technology Institute, Beijing, China","institution_ids":["https://openalex.org/I4210089056"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5103636162","display_name":"Zhiping Wen","orcid":null},"institutions":[{"id":"https://openalex.org/I4210089056","display_name":"Beijing Microelectronics Technology Institute","ror":"https://ror.org/007y7ej30","country_code":"CN","type":"other","lineage":["https://openalex.org/I4210089056"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhiping Wen","raw_affiliation_strings":["Beijing Microelectronics Technology Institute, Beijing, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Beijing Microelectronics Technology Institute, Beijing, China","institution_ids":["https://openalex.org/I4210089056"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"254","last_page":"254"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9955999851226807,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8117643594741821},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.6538432240486145},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6141219139099121},{"id":"https://openalex.org/keywords/test-vector","display_name":"Test vector","score":0.5790798664093018},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5183814167976379},{"id":"https://openalex.org/keywords/coordinate-system","display_name":"Coordinate system","score":0.4567576050758362},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.34919652342796326},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.304976224899292},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2534363865852356},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.1986987590789795}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8117643594741821},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.6538432240486145},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6141219139099121},{"id":"https://openalex.org/C100767440","wikidata":"https://www.wikidata.org/wiki/Q7705816","display_name":"Test vector","level":3,"score":0.5790798664093018},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5183814167976379},{"id":"https://openalex.org/C80551277","wikidata":"https://www.wikidata.org/wiki/Q11210","display_name":"Coordinate system","level":2,"score":0.4567576050758362},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.34919652342796326},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.304976224899292},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2534363865852356},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.1986987590789795},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C169903167","wikidata":"https://www.wikidata.org/wiki/Q3985153","display_name":"Test set","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2554688.2554740","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2554688.2554740","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2111241003","https://openalex.org/W2155019192","https://openalex.org/W2014709025","https://openalex.org/W2355315220","https://openalex.org/W4200391368","https://openalex.org/W2210979487","https://openalex.org/W2074043759","https://openalex.org/W3146360095","https://openalex.org/W2184011203","https://openalex.org/W1967468490"],"abstract_inverted_index":{"The":[0,124],"significance":[1],"of":[2,8,56,84,135],"FPGA":[3,18],"test":[4,45,52,101,126],"and":[5,30,79,95,174,189],"the":[6,23,39,72,81,114,121,133,158],"challenge":[7],"its":[9],"increasing":[10],"cost":[11],"can":[12,190],"never":[13],"be":[14,191],"ignored.":[15],"In":[16,141],"island-style":[17,197],"architectures,":[19],"hex":[20,28,31,57,85,91,109,136,144,146,162,187],"lines":[21,29,86,147,163],"are":[22,148],"principal":[24],"interconnect":[25,49,82,202],"resources.":[26],"Testing":[27],"Programmable":[32],"Interconnect":[33],"Points":[34],"(PIPs)":[35],"have":[36],"remained":[37],"as":[38,87],"major":[40],"technical":[41],"difficulty":[42],"in":[43,53,63,93,111,138],"FPGAs":[44,198],"due":[46],"to":[47,119,143,155,194],"complex":[48],"rules.":[50],"Particularly,":[51],"oblique":[54,112,139],"direction":[55],"PIPs":[58,92,110,137,188],"has":[59],"rarely":[60],"been":[61],"addressed":[62],"previous":[64,156],"studies.":[65],"Towards":[66],"this":[67,69,169],"challenge,":[68],"paper":[70],"for":[71,161,186],"first":[73],"time":[74],"proposes":[75],"a":[76,200],"coordinate":[77,106,115],"system":[78],"formulates":[80],"rules":[83],"mathematical":[88],"equations.":[89,107],"For":[90,108],"horizontal":[94],"vertical":[96],"direction,":[97,113],"an":[98],"efficient":[99],"circle":[100],"structure":[102,203],"is":[103,117,128,164],"formed":[104],"by":[105],"method":[116,170,181],"used":[118],"generate":[120],"partial-cascade":[122],"pattern.":[123],"corresponding":[125],"vector":[127],"also":[129,149],"generated,":[130],"which":[131],"ensures":[132],"ergodicity":[134],"direction.":[140],"addition":[142],"PIPs,":[145],"covered":[150],"without":[151],"extra":[152],"effort.":[153],"Compared":[154],"researches,":[157],"configuration":[159],"number":[160],"decreased":[165],"significantly.":[166],"We":[167],"evaluate":[168],"on":[171],"Xilinx":[172],"XC2V1000,":[173],"experimental":[175],"results":[176],"show":[177],"that":[178],"our":[179],"proposed":[180],"achieves":[182],"100%":[183],"fault":[184],"coverage":[185],"generally":[192],"applied":[193],"all":[195],"mainstream":[196],"with":[199],"similar":[201],"currently.":[204]},"counts_by_year":[],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
