{"id":"https://openalex.org/W1971346502","doi":"https://doi.org/10.1145/2554688.2554711","title":"A scalable routability-driven analytical placer with global router integration for FPGAs (abstract only)","display_name":"A scalable routability-driven analytical placer with global router integration for FPGAs (abstract only)","publication_year":2014,"publication_date":"2014-02-18","ids":{"openalex":"https://openalex.org/W1971346502","doi":"https://doi.org/10.1145/2554688.2554711","mag":"1971346502"},"language":"en","primary_location":{"id":"doi:10.1145/2554688.2554711","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2554688.2554711","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays","raw_type":"proceedings-article"},"type":"conference-abstract","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5040430392","display_name":"Ka Chun Lam","orcid":"https://orcid.org/0000-0003-2131-4386"},"institutions":[{"id":"https://openalex.org/I177725633","display_name":"Chinese University of Hong Kong","ror":"https://ror.org/00t33hh48","country_code":"HK","type":"education","lineage":["https://openalex.org/I177725633"]}],"countries":["HK"],"is_corresponding":false,"raw_author_name":"Ka Chun Lam","raw_affiliation_strings":["The Chinese University of Hong Kong, Hong Kong, Hong Kong"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"The Chinese University of Hong Kong, Hong Kong, Hong Kong","institution_ids":["https://openalex.org/I177725633"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103530103","display_name":"Wai-Chung Tang","orcid":null},"institutions":[{"id":"https://openalex.org/I166337079","display_name":"Queen Mary University of London","ror":"https://ror.org/026zzn846","country_code":"GB","type":"education","lineage":["https://openalex.org/I124357947","https://openalex.org/I166337079"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Wai-Chung Tang","raw_affiliation_strings":["Queen Mary University of London, London, England, UK","Queen Mary University of London, London, England, UK#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Queen Mary University of London, London, England, UK","institution_ids":["https://openalex.org/I166337079"]},{"raw_affiliation_string":"Queen Mary University of London, London, England, UK#TAB#","institution_ids":["https://openalex.org/I166337079"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5070795253","display_name":"Evangeline F. Y. Young","orcid":"https://orcid.org/0000-0003-0623-1590"},"institutions":[{"id":"https://openalex.org/I177725633","display_name":"Chinese University of Hong Kong","ror":"https://ror.org/00t33hh48","country_code":"HK","type":"education","lineage":["https://openalex.org/I177725633"]}],"countries":["HK"],"is_corresponding":false,"raw_author_name":"Evangeline F.Y. Young","raw_affiliation_strings":["The Chinese University of Hong Kong, Hong Kong, Hong Kong"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"The Chinese University of Hong Kong, Hong Kong, Hong Kong","institution_ids":["https://openalex.org/I177725633"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"242","last_page":"242"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/placement","display_name":"Placement","score":0.7744038105010986},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.7491884827613831},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.735023021697998},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7317504286766052},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7107440233230591},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.6980105042457581},{"id":"https://openalex.org/keywords/upper-and-lower-bounds","display_name":"Upper and lower bounds","score":0.6409666538238525},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5807108283042908},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.5436027646064758},{"id":"https://openalex.org/keywords/router","display_name":"Router","score":0.5088775157928467},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.31382277607917786},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2935802936553955},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.27744776010513306},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.22776895761489868},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.15818321704864502},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.1510820984840393},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.07848775386810303}],"concepts":[{"id":"https://openalex.org/C117690923","wikidata":"https://www.wikidata.org/wiki/Q1484784","display_name":"Placement","level":4,"score":0.7744038105010986},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.7491884827613831},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.735023021697998},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7317504286766052},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7107440233230591},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.6980105042457581},{"id":"https://openalex.org/C77553402","wikidata":"https://www.wikidata.org/wiki/Q13222579","display_name":"Upper and lower bounds","level":2,"score":0.6409666538238525},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5807108283042908},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.5436027646064758},{"id":"https://openalex.org/C2775896111","wikidata":"https://www.wikidata.org/wiki/Q642560","display_name":"Router","level":2,"score":0.5088775157928467},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.31382277607917786},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2935802936553955},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.27744776010513306},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.22776895761489868},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.15818321704864502},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1510820984840393},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.07848775386810303},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2554688.2554711","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2554688.2554711","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W1485756991","https://openalex.org/W2376218453","https://openalex.org/W1965055688","https://openalex.org/W2984236338","https://openalex.org/W3146360095","https://openalex.org/W2018147837","https://openalex.org/W2127180614","https://openalex.org/W1571681534","https://openalex.org/W2167711148","https://openalex.org/W2132668926"],"abstract_inverted_index":{"As":[0],"the":[1,39,48,54,76,87,90,95,102,107,120,134,145,150,184],"sizes":[2],"of":[3,44],"modern":[4],"circuits":[5,13],"become":[6],"bigger":[7],"and":[8,131,170,176],"bigger,":[9],"implementing":[10],"those":[11],"large":[12,172,234],"into":[14,133],"FPGA":[15,21,64],"becomes":[16],"arduous.":[17],"The":[18],"state-of-the-art":[19],"academic":[20],"place-and-route":[22],"tool,":[23],"VPR,":[24],"has":[25],"good":[26],"quality":[27],"but":[28],"needs":[29],"around":[30],"a":[31,36,59,155,197],"whole":[32],"day":[33],"to":[34,148,157],"complete":[35],"placement":[37,55,61,121,198],"when":[38,219],"input":[40],"circuit":[41],"contains":[42],"millions":[43],"lookup":[45,239],"tables,":[46,240],"excluding":[47],"runtime":[49],"for":[50,63,174],"routing.":[51],"To":[52],"expedite":[53],"process,":[56],"we":[57],"propose":[58],"routability-driven":[60],"algorithm":[62],"that":[65,181],"adopts":[66],"techniques":[67],"used":[68],"in":[69,81,119,144,160,207,216,232,245],"ASIC":[70,82],"global":[71,139],"placer.":[72],"Our":[73,224],"placer":[74],"follows":[75],"lower-bound-and-upper-bound":[77],"iterative":[78],"optimization":[79],"process":[80],"placers":[83],"like":[84],"Ripple.":[85],"In":[86,106],"lower-bound":[88,136],"computation,":[89,109],"total":[91],"HPWL,":[92],"modeled":[93],"using":[94,101,166],"Bound2Bound":[96],"net":[97],"model,":[98],"is":[99,113,189,221,226],"minimized":[100],"conjugate":[103],"gradient":[104],"method.":[105],"upper-bound":[108,146],"an":[110],"almost-legalized":[111],"result":[112,199],"produced":[114],"by":[115],"spreading":[116],"cells":[117],"linearly":[118],"area.":[122],"Those":[123],"positions":[124],"are":[125],"then":[126],"served":[127],"as":[128,154],"fixed-point":[129],"anchors":[130],"fed":[132],"next":[135],"computation.":[137],"Furthermore,":[138],"routing":[140,151],"will":[141],"be":[142],"performed":[143],"computation":[147],"estimate":[149],"segment":[152],"usage,":[153],"mean":[156],"consider":[158],"congestion":[159,220],"placement.":[161],"We":[162],"tested":[163],"our":[164,193],"approach":[165,194,225],"20":[167],"MCNC":[168],"benchmarks":[169,173,235],"4":[171],"performance":[175],"scalability.":[177],"Experimental":[178],"results":[179],"show":[180],"based":[182],"on":[183],"island-style":[185],"architecture":[186],"which":[187],"VPR":[188,203,231],"most":[190],"optimized":[191],"for,":[192],"can":[195],"obtain":[196],"8x":[200],"faster":[201,212,229],"than":[202,230],"with":[204,213,236,241],"2%":[205],"more":[206,215,244],"channel":[208,217,246],"width,":[209],"or":[210],"3x":[211],"1%":[214],"width":[218],"being":[222],"considered.":[223],"even":[227],"14x":[228],"placing":[233],"over":[237],"10,000":[238],"only":[242],"7%":[243],"width.":[247]},"counts_by_year":[],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
