{"id":"https://openalex.org/W2096835107","doi":"https://doi.org/10.1145/2504905","title":"In-network monitoring and control policy for DVFS of CMP networks-on-chip and last level caches","display_name":"In-network monitoring and control policy for DVFS of CMP networks-on-chip and last level caches","publication_year":2013,"publication_date":"2013-10-01","ids":{"openalex":"https://openalex.org/W2096835107","doi":"https://doi.org/10.1145/2504905","mag":"2096835107"},"language":"en","primary_location":{"id":"doi:10.1145/2504905","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2504905","pdf_url":null,"source":{"id":"https://openalex.org/S105046310","display_name":"ACM Transactions on Design Automation of Electronic Systems","issn_l":"1084-4309","issn":["1084-4309","1557-7309"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Design Automation of Electronic Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100329931","display_name":"Xi Chen","orcid":"https://orcid.org/0000-0002-3135-4114"},"institutions":[{"id":"https://openalex.org/I91045830","display_name":"Texas A&M University","ror":"https://ror.org/01f5ytq51","country_code":"US","type":"education","lineage":["https://openalex.org/I91045830"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Xi Chen","raw_affiliation_strings":["Texas A&amp;M University, College Station, TX","Texas A&M University, College Station. TX#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Texas A&amp;M University, College Station, TX","institution_ids":["https://openalex.org/I91045830"]},{"raw_affiliation_string":"Texas A&M University, College Station. TX#TAB#","institution_ids":["https://openalex.org/I91045830"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101651952","display_name":"Zheng Xu","orcid":"https://orcid.org/0000-0002-9811-2646"},"institutions":[{"id":"https://openalex.org/I91045830","display_name":"Texas A&M University","ror":"https://ror.org/01f5ytq51","country_code":"US","type":"education","lineage":["https://openalex.org/I91045830"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Zheng Xu","raw_affiliation_strings":["Texas A&amp;M University, College Station, TX","Texas A&M University, College Station. TX#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Texas A&amp;M University, College Station, TX","institution_ids":["https://openalex.org/I91045830"]},{"raw_affiliation_string":"Texas A&M University, College Station. TX#TAB#","institution_ids":["https://openalex.org/I91045830"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100388393","display_name":"Hyungjun Kim","orcid":"https://orcid.org/0009-0003-5078-4405"},"institutions":[{"id":"https://openalex.org/I91045830","display_name":"Texas A&M University","ror":"https://ror.org/01f5ytq51","country_code":"US","type":"education","lineage":["https://openalex.org/I91045830"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Hyungjun Kim","raw_affiliation_strings":["Texas A&amp;M University, College Station, TX","Texas A&M University, College Station. TX#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Texas A&amp;M University, College Station, TX","institution_ids":["https://openalex.org/I91045830"]},{"raw_affiliation_string":"Texas A&M University, College Station. TX#TAB#","institution_ids":["https://openalex.org/I91045830"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5082578661","display_name":"Paul V. Gratz","orcid":"https://orcid.org/0000-0001-7120-7189"},"institutions":[{"id":"https://openalex.org/I91045830","display_name":"Texas A&M University","ror":"https://ror.org/01f5ytq51","country_code":"US","type":"education","lineage":["https://openalex.org/I91045830"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Paul Gratz","raw_affiliation_strings":["Texas A&amp;M University, College Station, TX","Texas A&M University, College Station. TX#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Texas A&amp;M University, College Station, TX","institution_ids":["https://openalex.org/I91045830"]},{"raw_affiliation_string":"Texas A&M University, College Station. TX#TAB#","institution_ids":["https://openalex.org/I91045830"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103246390","display_name":"Jiang Hu","orcid":"https://orcid.org/0000-0003-1157-7799"},"institutions":[{"id":"https://openalex.org/I91045830","display_name":"Texas A&M University","ror":"https://ror.org/01f5ytq51","country_code":"US","type":"education","lineage":["https://openalex.org/I91045830"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jiang Hu","raw_affiliation_strings":["Texas A&amp;M University, College Station, TX","Texas A&M University, College Station. TX#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Texas A&amp;M University, College Station, TX","institution_ids":["https://openalex.org/I91045830"]},{"raw_affiliation_string":"Texas A&M University, College Station. TX#TAB#","institution_ids":["https://openalex.org/I91045830"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5007256099","display_name":"Michael Kishinevsky","orcid":"https://orcid.org/0000-0002-5593-9694"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Michael Kishinevsky","raw_affiliation_strings":["Strategic CAD Labs, Intel Corporation, Hillsboro, OR","Strategic CAD Laboratories, Intel Corporation, Hillsboro, OR"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Strategic CAD Labs, Intel Corporation, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Strategic CAD Laboratories, Intel Corporation, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5084255924","display_name":"\u00dcmit Y. Ogras","orcid":"https://orcid.org/0000-0002-5045-5535"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Umit Ogras","raw_affiliation_strings":["Strategic CAD Labs, Intel Corporation, Hillsboro, OR","Strategic CAD Laboratories, Intel Corporation, Hillsboro, OR"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Strategic CAD Labs, Intel Corporation, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Strategic CAD Laboratories, Intel Corporation, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":7,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":3.3954,"has_fulltext":false,"cited_by_count":30,"citation_normalized_percentile":{"value":0.93135855,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":"18","issue":"4","first_page":"1","last_page":"21"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10179","display_name":"Supercapacitor Materials and Fabrication","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/2504","display_name":"Electronic, Optical and Magnetic Materials"},"field":{"id":"https://openalex.org/fields/25","display_name":"Materials Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.996399998664856,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8405013084411621},{"id":"https://openalex.org/keywords/frequency-scaling","display_name":"Frequency scaling","score":0.6726604104042053},{"id":"https://openalex.org/keywords/parsec","display_name":"Parsec","score":0.6701381206512451},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.5338194370269775},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5284844636917114},{"id":"https://openalex.org/keywords/memory-hierarchy","display_name":"Memory hierarchy","score":0.4943509101867676},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.48474618792533875},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.45749175548553467},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.43709924817085266},{"id":"https://openalex.org/keywords/systemc","display_name":"SystemC","score":0.4345332384109497},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.4211358428001404},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.3534657061100006},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.3404504954814911},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.29115384817123413},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.22090116143226624},{"id":"https://openalex.org/keywords/channel","display_name":"Channel (broadcasting)","score":0.11292266845703125},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.10663452744483948}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8405013084411621},{"id":"https://openalex.org/C157742956","wikidata":"https://www.wikidata.org/wiki/Q3237776","display_name":"Frequency scaling","level":3,"score":0.6726604104042053},{"id":"https://openalex.org/C44060867","wikidata":"https://www.wikidata.org/wiki/Q12129","display_name":"Parsec","level":3,"score":0.6701381206512451},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.5338194370269775},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5284844636917114},{"id":"https://openalex.org/C2778100165","wikidata":"https://www.wikidata.org/wiki/Q1589327","display_name":"Memory hierarchy","level":3,"score":0.4943509101867676},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.48474618792533875},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.45749175548553467},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.43709924817085266},{"id":"https://openalex.org/C2776928060","wikidata":"https://www.wikidata.org/wiki/Q1753563","display_name":"SystemC","level":2,"score":0.4345332384109497},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.4211358428001404},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.3534657061100006},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.3404504954814911},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.29115384817123413},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.22090116143226624},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.11292266845703125},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.10663452744483948},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C31972630","wikidata":"https://www.wikidata.org/wiki/Q844240","display_name":"Computer vision","level":1,"score":0.0},{"id":"https://openalex.org/C150846664","wikidata":"https://www.wikidata.org/wiki/Q7602306","display_name":"Stars","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2504905","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2504905","pdf_url":null,"source":{"id":"https://openalex.org/S105046310","display_name":"ACM Transactions on Design Automation of Electronic Systems","issn_l":"1084-4309","issn":["1084-4309","1557-7309"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM Transactions on Design Automation of Electronic Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8999999761581421}],"awards":[],"funders":[{"id":"https://openalex.org/F4320307102","display_name":"Intel Corporation","ror":"https://ror.org/01ek73717"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":33,"referenced_works":["https://openalex.org/W590095378","https://openalex.org/W1532156674","https://openalex.org/W1833719054","https://openalex.org/W1980699667","https://openalex.org/W1985018624","https://openalex.org/W2018537611","https://openalex.org/W2053794660","https://openalex.org/W2058135584","https://openalex.org/W2077505860","https://openalex.org/W2080418535","https://openalex.org/W2081883574","https://openalex.org/W2093411808","https://openalex.org/W2103028594","https://openalex.org/W2116981307","https://openalex.org/W2120052218","https://openalex.org/W2122547471","https://openalex.org/W2123415020","https://openalex.org/W2128398793","https://openalex.org/W2129763083","https://openalex.org/W2136325278","https://openalex.org/W2139124612","https://openalex.org/W2142598547","https://openalex.org/W2149935279","https://openalex.org/W2151157308","https://openalex.org/W2158684546","https://openalex.org/W2161621274","https://openalex.org/W2166678275","https://openalex.org/W2166834317","https://openalex.org/W2169875292","https://openalex.org/W2224167729","https://openalex.org/W2464177207","https://openalex.org/W2493781403","https://openalex.org/W4241330137"],"related_works":["https://openalex.org/W3198758847","https://openalex.org/W4230458348","https://openalex.org/W2033923590","https://openalex.org/W2517347894","https://openalex.org/W2376124569","https://openalex.org/W2071013889","https://openalex.org/W1581055755","https://openalex.org/W2372348522","https://openalex.org/W2135667768","https://openalex.org/W2387047473"],"abstract_inverted_index":{"In":[0,47],"chip":[1],"design":[2],"today":[3],"and":[4,12,33,41,59,85,112,124],"for":[5,38,96],"a":[6,22,51,63,139,144],"foreseeable":[7],"future,":[8],"the":[9,56,60,70,76,79,83,93],"last-level":[10,44],"cache":[11],"on-chip":[13],"interconnect":[14],"is":[15,67,99],"not":[16],"only":[17],"performance":[18],"critical":[19],"but":[20],"also":[21],"substantial":[23],"power":[24],"consumer.":[25],"This":[26,73],"work":[27],"focuses":[28],"on":[29,130,135,147],"employing":[30],"dynamic":[31],"voltage":[32],"frequency":[34],"scaling":[35],"(DVFS)":[36],"policies":[37],"networks-on-chip":[39],"(NoC)":[40],"shared,":[42],"distributed":[43,57,110],"caches":[45],"(LLC).":[46],"particular,":[48],"we":[49],"consider":[50],"practical":[52],"system":[53,148],"architecture":[54,74,98],"where":[55],"LLC":[58],"NoC":[61],"share":[62],"voltage/frequency":[64],"domain":[65],"that":[66],"separate":[68],"from":[69],"core":[71],"domain.":[72],"enables":[75],"control":[77,132],"of":[78],"relative":[80],"speed":[81],"between":[82],"cores":[84],"memory":[86,118],"hierarchy":[87],"without":[88],"introducing":[89],"synchronization":[90],"delays":[91],"within":[92],"NoC.":[94],"DVFS":[95,105,128],"this":[97],"more":[100],"complex":[101],"than":[102],"individual":[103],"link/core-based":[104],"since":[106],"it":[107,126],"involves":[108],"spatially":[109],"monitoring":[111,122],"control.":[113],"We":[114],"propose":[115],"an":[116],"average":[117],"access":[119],"time":[120],"(AMAT)-based":[121],"technique":[123],"integrate":[125],"with":[127,143],"based":[129],"PID":[131],"theory.":[133],"Simulations":[134],"PARSEC":[136],"benchmarks":[137],"yield":[138],"27%":[140],"energy":[141],"savings":[142],"negligible":[145],"impact":[146],"performance.":[149]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":4},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":6},{"year":2016,"cited_by_count":4},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":3}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
