{"id":"https://openalex.org/W2052209990","doi":"https://doi.org/10.1145/2490302.2490309","title":"FPGA implementation of a novel DCT architecture reducing constant cosine terms","display_name":"FPGA implementation of a novel DCT architecture reducing constant cosine terms","publication_year":2013,"publication_date":"2013-05-29","ids":{"openalex":"https://openalex.org/W2052209990","doi":"https://doi.org/10.1145/2490302.2490309","mag":"2052209990"},"language":"en","primary_location":{"id":"doi:10.1145/2490302.2490309","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2490302.2490309","pdf_url":null,"source":{"id":"https://openalex.org/S4210193905","display_name":"ACM SIGARCH Computer Architecture News","issn_l":"0163-5964","issn":["0163-5964","1943-5851"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320740","host_organization_name":"ACM SIGARCH","host_organization_lineage":["https://openalex.org/P4310320740"],"host_organization_lineage_names":["ACM SIGARCH"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM SIGARCH Computer Architecture News","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5090241159","display_name":"Santanu Pal","orcid":"https://orcid.org/0000-0001-5040-4845"},"institutions":[{"id":"https://openalex.org/I99601430","display_name":"Maulana Abul Kalam Azad University of Technology, West Bengal","ror":"https://ror.org/030tcae29","country_code":"IN","type":"education","lineage":["https://openalex.org/I99601430"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Santanu Pal","raw_affiliation_strings":["West Bengal University of Technology, Kolkata, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"West Bengal University of Technology, Kolkata, India","institution_ids":["https://openalex.org/I99601430"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103229333","display_name":"Amitabha Sinha","orcid":"https://orcid.org/0000-0002-2179-209X"},"institutions":[{"id":"https://openalex.org/I99601430","display_name":"Maulana Abul Kalam Azad University of Technology, West Bengal","ror":"https://ror.org/030tcae29","country_code":"IN","type":"education","lineage":["https://openalex.org/I99601430"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Amitabha Sinha","raw_affiliation_strings":["West Bengal University of Technology, Kolkata, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"West Bengal University of Technology, Kolkata, India","institution_ids":["https://openalex.org/I99601430"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5110703198","display_name":"Pijush Biswas","orcid":null},"institutions":[{"id":"https://openalex.org/I99601430","display_name":"Maulana Abul Kalam Azad University of Technology, West Bengal","ror":"https://ror.org/030tcae29","country_code":"IN","type":"education","lineage":["https://openalex.org/I99601430"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Pijush Biswas","raw_affiliation_strings":["West Bengal University of Technology, Kolkata, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"West Bengal University of Technology, Kolkata, India","institution_ids":["https://openalex.org/I99601430"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.12049654,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"41","issue":"2","first_page":"36","last_page":"40"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.994700014591217,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9940000176429749,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/discrete-cosine-transform","display_name":"Discrete cosine transform","score":0.8637940883636475},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6084997653961182},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6038437485694885},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.5592632293701172},{"id":"https://openalex.org/keywords/constant","display_name":"Constant (computer programming)","score":0.47332367300987244},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.45283082127571106},{"id":"https://openalex.org/keywords/modified-discrete-cosine-transform","display_name":"Modified discrete cosine transform","score":0.43543773889541626},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.4332118630409241},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.36119353771209717},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2726699709892273},{"id":"https://openalex.org/keywords/transform-coding","display_name":"Transform coding","score":0.259986937046051},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.21471568942070007},{"id":"https://openalex.org/keywords/image","display_name":"Image (mathematics)","score":0.12414610385894775},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.10920804738998413}],"concepts":[{"id":"https://openalex.org/C2221639","wikidata":"https://www.wikidata.org/wiki/Q2877","display_name":"Discrete cosine transform","level":3,"score":0.8637940883636475},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6084997653961182},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6038437485694885},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5592632293701172},{"id":"https://openalex.org/C2777027219","wikidata":"https://www.wikidata.org/wiki/Q1284190","display_name":"Constant (computer programming)","level":2,"score":0.47332367300987244},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.45283082127571106},{"id":"https://openalex.org/C28726691","wikidata":"https://www.wikidata.org/wiki/Q1268231","display_name":"Modified discrete cosine transform","level":5,"score":0.43543773889541626},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.4332118630409241},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.36119353771209717},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2726699709892273},{"id":"https://openalex.org/C169805256","wikidata":"https://www.wikidata.org/wiki/Q1361381","display_name":"Transform coding","level":4,"score":0.259986937046051},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.21471568942070007},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.12414610385894775},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.10920804738998413},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2490302.2490309","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2490302.2490309","pdf_url":null,"source":{"id":"https://openalex.org/S4210193905","display_name":"ACM SIGARCH Computer Architecture News","issn_l":"0163-5964","issn":["0163-5964","1943-5851"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310320740","host_organization_name":"ACM SIGARCH","host_organization_lineage":["https://openalex.org/P4310320740"],"host_organization_lineage_names":["ACM SIGARCH"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ACM SIGARCH Computer Architecture News","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6700000166893005,"display_name":"Sustainable cities and communities","id":"https://metadata.un.org/sdg/11"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W174575216","https://openalex.org/W1586616317","https://openalex.org/W1967579297","https://openalex.org/W2098052318","https://openalex.org/W2127996712","https://openalex.org/W2155235999","https://openalex.org/W2158296060","https://openalex.org/W2311654837"],"related_works":["https://openalex.org/W2565123265","https://openalex.org/W2090071970","https://openalex.org/W2112852877","https://openalex.org/W2128618986","https://openalex.org/W2108727544","https://openalex.org/W1507290937","https://openalex.org/W2111266495","https://openalex.org/W2162505377","https://openalex.org/W1963903148","https://openalex.org/W2363607146"],"abstract_inverted_index":{"This":[0,36],"paper":[1],"presents":[2],"a":[3],"new":[4],"scalable":[5,47],"architecture":[6,21,45,59],"for":[7],"Discrete":[8],"Cosine":[9],"Transform":[10],"(DCT).":[11],"In":[12],"contrast":[13],"to":[14,53],"the":[15,19,23,30,41],"conventional":[16],"DCT":[17],"architecture,":[18],"proposed":[20],"reduces":[22,40],"number":[24],"of":[25],"constant":[26],"cosine":[27],"terms":[28],"using":[29],"matrix":[31],"transposition":[32],"and":[33,48],"symmetry":[34],"property.":[35],"in":[37],"turn,":[38],"considerably":[39],"computation":[42],"time.":[43],"The":[44,58],"is":[46],"it":[49],"can":[50],"be":[51],"extended":[52],"support":[54],"any":[55],"transform":[56],"length.":[57],"was":[60],"validated":[61],"on":[62],"Xilinx":[63],"Vertex-4":[64],"FPGA.":[65]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
