{"id":"https://openalex.org/W2030158277","doi":"https://doi.org/10.1145/2483028.2483122","title":"A memory mapping approach for network and controller optimization in parallel interleaver architectures","display_name":"A memory mapping approach for network and controller optimization in parallel interleaver architectures","publication_year":2013,"publication_date":"2013-05-02","ids":{"openalex":"https://openalex.org/W2030158277","doi":"https://doi.org/10.1145/2483028.2483122","mag":"2030158277"},"language":"en","primary_location":{"id":"doi:10.1145/2483028.2483122","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2483028.2483122","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5074364346","display_name":"Aroua Briki","orcid":null},"institutions":[{"id":"https://openalex.org/I161929037","display_name":"Universit\u00e9 de Bretagne Occidentale","ror":"https://ror.org/01b8h3982","country_code":"FR","type":"education","lineage":["https://openalex.org/I161929037"]},{"id":"https://openalex.org/I2802204017","display_name":"Universit\u00e9 de Bretagne Sud","ror":"https://ror.org/04ed7fw48","country_code":"FR","type":"education","lineage":["https://openalex.org/I2802204017"]},{"id":"https://openalex.org/I4210123702","display_name":"Laboratoire des Sciences et Techniques de l\u2019Information de la Communication et de la Connaissance","ror":"https://ror.org/0266kfd37","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I180375564","https://openalex.org/I201181511","https://openalex.org/I205703379","https://openalex.org/I2802204017","https://openalex.org/I4210123702","https://openalex.org/I4210127572","https://openalex.org/I4210145102","https://openalex.org/I4210148559","https://openalex.org/I4210159245","https://openalex.org/I4405260085"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Aroua Briki","raw_affiliation_strings":["Universit\u00e9 de Bretagne Sud / Lab-STICC, Lorient, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Universit\u00e9 de Bretagne Sud / Lab-STICC, Lorient, France","institution_ids":["https://openalex.org/I161929037","https://openalex.org/I2802204017","https://openalex.org/I4210123702"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5078027340","display_name":"Cyrille Chavet","orcid":"https://orcid.org/0000-0002-7993-4628"},"institutions":[{"id":"https://openalex.org/I161929037","display_name":"Universit\u00e9 de Bretagne Occidentale","ror":"https://ror.org/01b8h3982","country_code":"FR","type":"education","lineage":["https://openalex.org/I161929037"]},{"id":"https://openalex.org/I2802204017","display_name":"Universit\u00e9 de Bretagne Sud","ror":"https://ror.org/04ed7fw48","country_code":"FR","type":"education","lineage":["https://openalex.org/I2802204017"]},{"id":"https://openalex.org/I4210123702","display_name":"Laboratoire des Sciences et Techniques de l\u2019Information de la Communication et de la Connaissance","ror":"https://ror.org/0266kfd37","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I180375564","https://openalex.org/I201181511","https://openalex.org/I205703379","https://openalex.org/I2802204017","https://openalex.org/I4210123702","https://openalex.org/I4210127572","https://openalex.org/I4210145102","https://openalex.org/I4210148559","https://openalex.org/I4210159245","https://openalex.org/I4405260085"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Cyrille Chavet","raw_affiliation_strings":["Universit\u00e9 de Bretagne Sud / Lab-STICC, Lorient, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Universit\u00e9 de Bretagne Sud / Lab-STICC, Lorient, France","institution_ids":["https://openalex.org/I161929037","https://openalex.org/I2802204017","https://openalex.org/I4210123702"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5004215191","display_name":"Philippe Coussy","orcid":"https://orcid.org/0000-0002-7222-5271"},"institutions":[{"id":"https://openalex.org/I161929037","display_name":"Universit\u00e9 de Bretagne Occidentale","ror":"https://ror.org/01b8h3982","country_code":"FR","type":"education","lineage":["https://openalex.org/I161929037"]},{"id":"https://openalex.org/I2802204017","display_name":"Universit\u00e9 de Bretagne Sud","ror":"https://ror.org/04ed7fw48","country_code":"FR","type":"education","lineage":["https://openalex.org/I2802204017"]},{"id":"https://openalex.org/I4210123702","display_name":"Laboratoire des Sciences et Techniques de l\u2019Information de la Communication et de la Connaissance","ror":"https://ror.org/0266kfd37","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I180375564","https://openalex.org/I201181511","https://openalex.org/I205703379","https://openalex.org/I2802204017","https://openalex.org/I4210123702","https://openalex.org/I4210127572","https://openalex.org/I4210145102","https://openalex.org/I4210148559","https://openalex.org/I4210159245","https://openalex.org/I4405260085"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Philippe Coussy","raw_affiliation_strings":["Universit\u00e9 de Bretagne Sud / Lab-STICC, Lorient, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Universit\u00e9 de Bretagne Sud / Lab-STICC, Lorient, France","institution_ids":["https://openalex.org/I161929037","https://openalex.org/I2802204017","https://openalex.org/I4210123702"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.12392191,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"38","issue":null,"first_page":"321","last_page":"322"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11321","display_name":"Error Correcting Code Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11321","display_name":"Error Correcting Code Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8059390783309937},{"id":"https://openalex.org/keywords/interleaving","display_name":"Interleaving","score":0.7021422386169434},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.5265336632728577},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5100319981575012},{"id":"https://openalex.org/keywords/controller","display_name":"Controller (irrigation)","score":0.4820445477962494},{"id":"https://openalex.org/keywords/shared-memory","display_name":"Shared memory","score":0.4738735854625702},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.42516955733299255},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.3792034983634949},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3755767345428467},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.27007636427879333},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.1874164640903473},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.15909820795059204}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8059390783309937},{"id":"https://openalex.org/C28034677","wikidata":"https://www.wikidata.org/wiki/Q17092530","display_name":"Interleaving","level":2,"score":0.7021422386169434},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.5265336632728577},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5100319981575012},{"id":"https://openalex.org/C203479927","wikidata":"https://www.wikidata.org/wiki/Q5165939","display_name":"Controller (irrigation)","level":2,"score":0.4820445477962494},{"id":"https://openalex.org/C133875982","wikidata":"https://www.wikidata.org/wiki/Q764810","display_name":"Shared memory","level":2,"score":0.4738735854625702},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.42516955733299255},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.3792034983634949},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3755767345428467},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.27007636427879333},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.1874164640903473},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.15909820795059204},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C6557445","wikidata":"https://www.wikidata.org/wiki/Q173113","display_name":"Agronomy","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2483028.2483122","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2483028.2483122","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/16","score":0.6800000071525574,"display_name":"Peace, Justice and strong institutions"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1964471164","https://openalex.org/W1994302772","https://openalex.org/W2004695592","https://openalex.org/W2030994586","https://openalex.org/W2122851544","https://openalex.org/W2149862204","https://openalex.org/W2483616100","https://openalex.org/W2949989006"],"related_works":["https://openalex.org/W1655266410","https://openalex.org/W2389051085","https://openalex.org/W2330343234","https://openalex.org/W1901012776","https://openalex.org/W2463883322","https://openalex.org/W2229382548","https://openalex.org/W2391789612","https://openalex.org/W2814468324","https://openalex.org/W2389236462","https://openalex.org/W1614034078"],"abstract_inverted_index":{"Recent":[0],"communication":[1],"standards":[2],"and":[3,48,78,81],"storage":[4],"systems":[5],"uses":[6],"parallel":[7,24],"architectures":[8,25],"for":[9,44],"error":[10],"correcting":[11],"codes":[12],"(LDPC":[13],"or":[14],"Turbo-codes)":[15],"to":[16,64],"reliably":[17],"transfer":[18],"data":[19],"between":[20],"two":[21],"equipments.":[22],"However,":[23],"suffer":[26],"from":[27],"memory":[28,42,82],"access":[29],"conflicts.":[30],"In":[31],"this":[32],"paper,":[33],"we":[34],"present":[35],"a":[36,40],"method":[37],"that":[38],"finds":[39],"conflict-free":[41],"mapping":[43],"any":[45,49],"interleaving":[46],"law":[47],"parallelism.":[50],"The":[51],"proposed":[52],"approach":[53],"always":[54],"complies":[55],"with":[56],"the":[57,61,67,74],"interconnection":[58],"network":[59,77],"topology":[60],"designer":[62],"wants":[63],"infer.":[65],"Moreover,":[66],"resulting":[68],"architecture":[69],"is":[70],"optimized":[71],"by":[72],"reducing":[73],"cost":[75],"of":[76],"controller":[79],"(network":[80],"controller)":[83],"architectures.":[84]},"counts_by_year":[],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}