{"id":"https://openalex.org/W2025094923","doi":"https://doi.org/10.1145/2483028.2483100","title":"Analysis of the area-delay performance of hybrid nanoelectronic memory cores used in field programmable gate arrays","display_name":"Analysis of the area-delay performance of hybrid nanoelectronic memory cores used in field programmable gate arrays","publication_year":2013,"publication_date":"2013-05-02","ids":{"openalex":"https://openalex.org/W2025094923","doi":"https://doi.org/10.1145/2483028.2483100","mag":"2025094923"},"language":"en","primary_location":{"id":"doi:10.1145/2483028.2483100","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2483028.2483100","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101848223","display_name":"Qin Wang","orcid":"https://orcid.org/0009-0005-4596-1918"},"institutions":[{"id":"https://openalex.org/I887968799","display_name":"RWTH Aachen University","ror":"https://ror.org/04xfq0f34","country_code":"DE","type":"education","lineage":["https://openalex.org/I887968799"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Qin Wang","raw_affiliation_strings":["RWTH Aachen University, Aachen, Germany","RWTH-Aachen University, Aachen, Germany"],"affiliations":[{"raw_affiliation_string":"RWTH Aachen University, Aachen, Germany","institution_ids":["https://openalex.org/I887968799"]},{"raw_affiliation_string":"RWTH-Aachen University, Aachen, Germany","institution_ids":["https://openalex.org/I887968799"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5033971238","display_name":"Arne Heittmann","orcid":null},"institutions":[{"id":"https://openalex.org/I887968799","display_name":"RWTH Aachen University","ror":"https://ror.org/04xfq0f34","country_code":"DE","type":"education","lineage":["https://openalex.org/I887968799"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Arne Heittmann","raw_affiliation_strings":["RWTH Aachen University, Aachen, Germany","RWTH-Aachen University, Aachen, Germany"],"affiliations":[{"raw_affiliation_string":"RWTH Aachen University, Aachen, Germany","institution_ids":["https://openalex.org/I887968799"]},{"raw_affiliation_string":"RWTH-Aachen University, Aachen, Germany","institution_ids":["https://openalex.org/I887968799"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5103870395","display_name":"Tobias G. Noll","orcid":null},"institutions":[{"id":"https://openalex.org/I887968799","display_name":"RWTH Aachen University","ror":"https://ror.org/04xfq0f34","country_code":"DE","type":"education","lineage":["https://openalex.org/I887968799"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Tobias G. Noll","raw_affiliation_strings":["RWTH Aachen University, Aachen, Germany","RWTH-Aachen University, Aachen, Germany"],"affiliations":[{"raw_affiliation_string":"RWTH Aachen University, Aachen, Germany","institution_ids":["https://openalex.org/I887968799"]},{"raw_affiliation_string":"RWTH-Aachen University, Aachen, Germany","institution_ids":["https://openalex.org/I887968799"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5101848223"],"corresponding_institution_ids":["https://openalex.org/I887968799"],"apc_list":null,"apc_paid":null,"fwci":0.2402,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.60390881,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"233","last_page":"238"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11601","display_name":"Neuroscience and Neural Engineering","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2804","display_name":"Cellular and Molecular Neuroscience"},"field":{"id":"https://openalex.org/fields/28","display_name":"Neuroscience"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.719873309135437},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5652019381523132},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5558891892433167},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.537557065486908},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5216717720031738},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.485347181558609},{"id":"https://openalex.org/keywords/metric","display_name":"Metric (unit)","score":0.4842917323112488},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.45874956250190735},{"id":"https://openalex.org/keywords/crossbar-switch","display_name":"Crossbar switch","score":0.437412291765213},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.31837546825408936},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.24120426177978516},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.22839593887329102}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.719873309135437},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5652019381523132},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5558891892433167},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.537557065486908},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5216717720031738},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.485347181558609},{"id":"https://openalex.org/C176217482","wikidata":"https://www.wikidata.org/wiki/Q860554","display_name":"Metric (unit)","level":2,"score":0.4842917323112488},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.45874956250190735},{"id":"https://openalex.org/C29984679","wikidata":"https://www.wikidata.org/wiki/Q1929149","display_name":"Crossbar switch","level":2,"score":0.437412291765213},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.31837546825408936},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.24120426177978516},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.22839593887329102},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1145/2483028.2483100","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2483028.2483100","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI","raw_type":"proceedings-article"},{"id":"pmh:oai:publications.rwth-aachen.de:227068","is_oa":false,"landing_page_url":"https://publications.rwth-aachen.de/record/227068","pdf_url":null,"source":{"id":"https://openalex.org/S4306401362","display_name":"RWTH Publications (RWTH Aachen)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I887968799","host_organization_name":"RWTH Aachen University","host_organization_lineage":["https://openalex.org/I887968799"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"The proceedings of the 2013 ACM international conference of the Great Lakes Symposium on VLSI 2013 : May 2 - 3, 2013, Paris, France / Jos\u00e9 L. Ayala<br/>2013 ACM international conference of the Great Lakes Symposium on VLSI 2013, Paris, France, 2013-05-02 - 2013-05-03","raw_type":"info:eu-repo/semantics/publishedVersion"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.49000000953674316}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W2009604146","https://openalex.org/W2031039947","https://openalex.org/W2032567996","https://openalex.org/W2074357625","https://openalex.org/W2113645429","https://openalex.org/W2120544688","https://openalex.org/W2120557145","https://openalex.org/W2142704184","https://openalex.org/W2157926305","https://openalex.org/W2165930573","https://openalex.org/W6681120143"],"related_works":["https://openalex.org/W2145932742","https://openalex.org/W1874409533","https://openalex.org/W2554791727","https://openalex.org/W1981395029","https://openalex.org/W2108083791","https://openalex.org/W4250137794","https://openalex.org/W2063341228","https://openalex.org/W2111673944","https://openalex.org/W2170979950","https://openalex.org/W1900707063"],"abstract_inverted_index":{"In":[0,46],"this":[1],"paper,":[2],"an":[3],"area-delay":[4],"metric":[5,112,127],"(AT)":[6],"of":[7,81,100,108,124],"hybrid":[8],"memristive/CMOS":[9],"memory":[10,16,44,115],"architectures":[11],"is":[12,32,134,157,173,181],"discussed.":[13],"The":[14,79],"proposed":[15],"circuit":[17,145],"can":[18],"be":[19],"used":[20],"as":[21,43],"a":[22,35,88,109,184],"lookup":[23],"table":[24],"in":[25,94],"field":[26],"programmable":[27],"gate":[28],"arrays":[29],"(FPGAs)":[30],"and":[31,76,92],"modeled":[33],"by":[34,136],"passive":[36],"nanoelectronic":[37],"crossbar":[38],"comprising":[39],"resistive":[40,48],"switches":[41,49],"(RS)":[42],"elements.":[45],"particular,":[47],"which":[50,103,133,180],"are":[51,59,66],"based":[52],"on":[53],"the":[54,62,82,97,106,114,122,125,130,137,143,151,168,176],"electrochemical":[55],"metallization":[56],"effect":[57],"(ECM)":[58],"assumed.":[60],"At":[61],"periphery,":[63],"CMOS":[64,83,90,139],"circuits":[65,140],"included":[67],"with":[68],"provide":[69],"appropriate":[70],"voltage":[71],"levels":[72],"for":[73,87,105,113,165,183],"robust":[74],"read":[75],"write":[77],"operations.":[78],"optimization":[80],"periphery":[84],"was":[85],"done":[86],"40-nm":[89],"technology,":[91],"especially":[93],"regard":[95],"to":[96],"physical":[98],"properties":[99],"ECM":[101],"cells":[102],"allows":[104],"derivation":[107],"realistic":[110],"AT":[111,126],"core":[116,187],"circuit.":[117,188],"For":[118],"different":[119],"architectural":[120],"choices,":[121],"evaluation":[123],"shows,":[128],"that":[129],"area":[131,154,170,177],"overhead":[132],"caused":[135],"peripheral":[138],"significantly":[141],"determines":[142],"total":[144],"area.":[146],"Under":[147],"almost":[148],"all":[149],"conditions":[150,167],"required":[152,182],"silicon":[153],"per":[155,171,178],"bit":[156,172,179],"far":[158],"beyond":[159],"4F2":[160],"(F:":[161],"lithographic":[162],"resolution),":[163],"but":[164],"particular":[166],"effective":[169],"smaller":[174],"than":[175],"corresponding":[185],"SRAM":[186]},"counts_by_year":[{"year":2014,"cited_by_count":1}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}
