{"id":"https://openalex.org/W2106952290","doi":"https://doi.org/10.1145/2483028.2483096","title":"Combating NBTI-induced aging in data caches","display_name":"Combating NBTI-induced aging in data caches","publication_year":2013,"publication_date":"2013-05-02","ids":{"openalex":"https://openalex.org/W2106952290","doi":"https://doi.org/10.1145/2483028.2483096","mag":"2106952290"},"language":"en","primary_location":{"id":"doi:10.1145/2483028.2483096","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2483028.2483096","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100328329","display_name":"Shuai Wang","orcid":"https://orcid.org/0000-0002-9862-3892"},"institutions":[{"id":"https://openalex.org/I881766915","display_name":"Nanjing University","ror":"https://ror.org/01rxvg760","country_code":"CN","type":"education","lineage":["https://openalex.org/I881766915"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Shuai Wang","raw_affiliation_strings":["Nanjing University, Nanjing, China"],"affiliations":[{"raw_affiliation_string":"Nanjing University, Nanjing, China","institution_ids":["https://openalex.org/I881766915"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5089359190","display_name":"Guangshan Duan","orcid":null},"institutions":[{"id":"https://openalex.org/I881766915","display_name":"Nanjing University","ror":"https://ror.org/01rxvg760","country_code":"CN","type":"education","lineage":["https://openalex.org/I881766915"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Guangshan Duan","raw_affiliation_strings":["Nanjing University, Nanjing, China"],"affiliations":[{"raw_affiliation_string":"Nanjing University, Nanjing, China","institution_ids":["https://openalex.org/I881766915"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5012812762","display_name":"Chuanlei Zheng","orcid":"https://orcid.org/0000-0002-7317-826X"},"institutions":[{"id":"https://openalex.org/I881766915","display_name":"Nanjing University","ror":"https://ror.org/01rxvg760","country_code":"CN","type":"education","lineage":["https://openalex.org/I881766915"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Chuanlei Zheng","raw_affiliation_strings":["Nanjing University, Nanjing, China"],"affiliations":[{"raw_affiliation_string":"Nanjing University, Nanjing, China","institution_ids":["https://openalex.org/I881766915"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101981715","display_name":"Tao Jin","orcid":"https://orcid.org/0009-0007-6589-0656"},"institutions":[{"id":"https://openalex.org/I881766915","display_name":"Nanjing University","ror":"https://ror.org/01rxvg760","country_code":"CN","type":"education","lineage":["https://openalex.org/I881766915"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Tao Jin","raw_affiliation_strings":["Nanjing University, Nanjing, China"],"affiliations":[{"raw_affiliation_string":"Nanjing University, Nanjing, China","institution_ids":["https://openalex.org/I881766915"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5100328329"],"corresponding_institution_ids":["https://openalex.org/I881766915"],"apc_list":null,"apc_paid":null,"fwci":1.8916,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":{"value":0.87471731,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"215","last_page":"220"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/negative-bias-temperature-instability","display_name":"Negative-bias temperature instability","score":0.7714183330535889},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.7542170286178589},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.7519051432609558},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6201279163360596},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.6158640384674072},{"id":"https://openalex.org/keywords/duty-cycle","display_name":"Duty cycle","score":0.6011381149291992},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.4710055887699127},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.4334464967250824},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.42264634370803833},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.36506664752960205},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.26803189516067505},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.2491641640663147},{"id":"https://openalex.org/keywords/mosfet","display_name":"MOSFET","score":0.23236745595932007},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.22735324501991272},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.16532790660858154},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.15670722723007202},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.14317283034324646},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.12475097179412842},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.10525020956993103}],"concepts":[{"id":"https://openalex.org/C557185","wikidata":"https://www.wikidata.org/wiki/Q6987194","display_name":"Negative-bias temperature instability","level":5,"score":0.7714183330535889},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.7542170286178589},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.7519051432609558},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6201279163360596},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.6158640384674072},{"id":"https://openalex.org/C199822604","wikidata":"https://www.wikidata.org/wiki/Q557120","display_name":"Duty cycle","level":3,"score":0.6011381149291992},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.4710055887699127},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.4334464967250824},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.42264634370803833},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.36506664752960205},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.26803189516067505},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.2491641640663147},{"id":"https://openalex.org/C2778413303","wikidata":"https://www.wikidata.org/wiki/Q210793","display_name":"MOSFET","level":4,"score":0.23236745595932007},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.22735324501991272},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.16532790660858154},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.15670722723007202},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.14317283034324646},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12475097179412842},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.10525020956993103},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/2483028.2483096","is_oa":false,"landing_page_url":"https://doi.org/10.1145/2483028.2483096","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8899999856948853,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":29,"referenced_works":["https://openalex.org/W1992606304","https://openalex.org/W1998654458","https://openalex.org/W2032094184","https://openalex.org/W2102727118","https://openalex.org/W2103792078","https://openalex.org/W2107562186","https://openalex.org/W2110027520","https://openalex.org/W2110999128","https://openalex.org/W2111664042","https://openalex.org/W2113115586","https://openalex.org/W2115016937","https://openalex.org/W2115194678","https://openalex.org/W2118657369","https://openalex.org/W2120466934","https://openalex.org/W2125169487","https://openalex.org/W2129817078","https://openalex.org/W2131054871","https://openalex.org/W2136066624","https://openalex.org/W2146787584","https://openalex.org/W2153456949","https://openalex.org/W2154451732","https://openalex.org/W2157468334","https://openalex.org/W2164406663","https://openalex.org/W2168116639","https://openalex.org/W3141284234","https://openalex.org/W3148731126","https://openalex.org/W3149855342","https://openalex.org/W4232837724","https://openalex.org/W4240146668"],"related_works":["https://openalex.org/W3150866391","https://openalex.org/W2112214579","https://openalex.org/W2310523918","https://openalex.org/W4200470254","https://openalex.org/W2517623286","https://openalex.org/W2071018290","https://openalex.org/W2186949690","https://openalex.org/W2167303720","https://openalex.org/W2154109900","https://openalex.org/W2497617944"],"abstract_inverted_index":{"The":[0],"negative":[1,104],"bias":[2],"temperature":[3],"instability":[4],"(NBTI)":[5],"in":[6,61,78,90,117],"CMOS":[7],"devices":[8],"is":[9,71],"one":[10],"of":[11,15,26,41,87,113,142,177],"most":[12],"prominent":[13],"sources":[14],"aging":[16,59,77,105,175],"mechanisms,":[17],"which":[18,167],"can":[19,146,160],"induce":[20],"severe":[21],"threats":[22],"to":[23,35,73,101,121],"the":[24,36,42,45,58,62,75,79,83,88,91,103,109,114,118,138,143,152,163,171],"reliability":[25],"modern":[27],"processors":[28],"at":[29],"deep":[30],"submicron":[31],"semiconductor":[32],"technologies.":[33],"Due":[34],"unbalanced":[37],"duty":[38,110,139],"cycle":[39,111,140],"ratio":[40,112,141],"SRAM":[43,115],"cells,":[44],"data":[46,63,80,92,144,178],"cache":[47,93,145],"suffers":[48],"a":[49],"heavy":[50],"NBTI":[51],"stress":[52],"and":[53,135,174],"this":[54,66],"will":[55,168],"further":[56,169],"exacerbate":[57],"effect":[60,176],"cache.":[64,81],"In":[65],"paper,":[67],"an":[68],"aging-aware":[69],"design":[70,159],"proposed":[72,100,129],"combat":[74],"NBTI-induced":[76],"First,":[82],"detailed":[84],"lifetime":[85,124],"behaviors":[86],"cachelines":[89,119],"are":[94,99],"studied.":[95],"Then,":[96],"different":[97,123],"schemes":[98],"mitigate":[102],"effects":[106],"by":[107],"balancing":[108],"cells":[116],"according":[120],"their":[122],"phases.":[125],"By":[126,150],"applying":[127],"our":[128,158],"idle-time-based":[130],"cacheline":[131],"invalidation,":[132],"early":[133],"write-back,":[134],"bit-flipping":[136],"schemes,":[137],"be":[147],"well":[148],"balanced.":[149],"adopting":[151],"drowsy":[153],"scheme":[154],"for":[155],"invalidated":[156],"cachelines,":[157],"also":[161],"reduce":[162],"power":[164],"consumption":[165],"significantly,":[166],"optimize":[170],"thermal":[172],"behavior":[173],"caches.":[179]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":3},{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}